MTB2P50E
Preferred Device
Power MOSFET
2 Amps, 500 Volts
P−Channel D
2
PAK
This high voltage MOSFET uses an advanced termination scheme
to provide enhanced voltage−blocking capability without degrading
performance over time. In addition, this Power MOSFET is designed
to withstand high energy in the avalanche and commutation modes.
The energy efficient design also offers a drain−to−source diode with a
fast recovery time. Designed for high voltage, high speed switching
applications in power supplies, converters and PWM motor controls,
these devices are particularly well suited for bridge circuits where
diode speed and commutating safe operating areas are critical and
offer additional safety margin against unexpected voltage transients.
Features
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2 AMPERES, 500 VOLTS
R
DS(on)
= 6
W
P−Channel
D
•
Robust High Voltage Termination
•
Avalanche Energy Specified
•
Source−to−Drain Diode Recovery Time Comparable to a Discrete
•
•
•
•
•
Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
I
DSS
and V
DS(on)
Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Pb−Free Package is Available
Rating
Drain−Source Voltage
Drain−Gate Voltage (R
GS
= 1.0 MW)
Gate−Source Voltage − Continuous
Non−Repetitive (t
p
≤
10 ms)
Drain Current − Continuous
Drain Current
− Continuous @ 100°C
Drain Current
− Single Pulse (t
p
≤
10
ms)
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ T
A
= 25°C (Note 1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 100 Vdc, V
GS
= 10 Vdc,
I
L
= 4.0 Apk, L = 10 mH, R
G
= 25
W)
Thermal Resistance
− Junction−to−Case
− Junction−to−Ambient
− Junction−to−Ambient (Note 1)
Maximum Lead Temperature for Soldering
Purposes, 1/8″ from case for 10 sec
Symbol
V
DSS
V
DGR
V
GS
V
GSM
I
D
I
D
I
DM
P
D
Value
500
500
±
20
±
40
2.0
1.6
6.0
75
0.6
2.5
−55 to
150
80
Unit
Vdc
Vdc
Vdc
Vpk
Adc
Apk
W
W/°C
°C
mJ
G
S
D
2
PAK
CASE 418B
STYLE 2
1
MAXIMUM RATINGS
(T
C
= 25°C unless otherwise noted)
MARKING DIAGRAM & PIN ASSIGNMENT
4
Drain
T
P50EG
AYWW
1
Gate
2
2
Drain
3
Source
T
J
, T
stg
E
AS
T2P50E
A
Y
WW
G
= Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
°C/W
R
qJC
R
qJA
R
qJA
T
L
1.67
62.5
50
260
°C
Device
MTB2P50ET4
MTB2P50ET4G
Package
D
2
PAK
D
2
PAK
(Pb−Free)
Shipping
†
800/Tape & Reel
800/Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. When surface mounted to an FR4 board using the minimum recommended
pad size.
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
June, 2006 − Rev. 4
Publication Order Number:
MTB2P50E/D
MTB2P50E
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Characteristic
OFF CHARACTERISTICS
Drain−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 500 Vdc, V
GS
= 0 Vdc)
(V
DS
= 500 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 2)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Temperature Coefficient (Negative)
Static Drain−Source On−Resistance (V
GS
= 10 Vdc, I
D
= 1.0 Adc)
Drain−Source On−Voltage (V
GS
= 10 Vdc)
(I
D
= 2.0 Adc)
(I
D
= 1.0 Adc, T
J
= 125°C)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 3)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge (See Figure 8)
(V
DS
= 400 Vdc, I
D
= 2.0 Adc, V
GS
= 10 Vdc)
(V
DD
= 250 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc, R
G
= 9.1
W)
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 2)
(I
S
= 2.0 Adc, V
GS
= 0 Vdc)
(I
S
= 2.0 Adc, V
GS
= 0 Vdc, T
J
= 125°C)
V
SD
−
−
t
rr
(I
S
= 2.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25″ from package to source bond pad)
2. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
3. Switching characteristics are independent of operating junction temperature.
L
D
−
L
S
−
4.5
7.5
−
−
nH
nH
t
a
t
b
Q
RR
−
−
−
−
2.3
1.85
223
161
62
1.92
3.5
−
−
−
−
−
mC
ns
Vdc
−
−
−
−
−
−
−
−
12
14
21
19
19
3.7
7.9
9.9
24
28
42
38
27
−
−
−
nC
ns
(V
DS
= 25 Vdc, V
GS
= 0 Vdc, f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
845
100
26
1183
140
52
pF
V
GS(th)
2.0
−
R
DS(on)
V
DS(on)
−
−
g
FS
1.5
9.5
−
2.9
14.4
12.6
−
mhos
−
3.0
4.0
4.5
4.0
−
6.0
Vdc
mV/°C
W
Vdc
V
(BR)DSS
500
−
I
DSS
−
−
I
GSS
−
−
−
−
10
100
100
nAdc
−
564
−
−
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
(See Figure 14)
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2
MTB2P50E
TYPICAL ELECTRICAL CHARACTERISTICS
4
I D , DRAIN CURRENT (AMPS)
I D , DRAIN CURRENT (AMPS)
3.5
3
2.5
2
1.5
1
0.5
4V
0
0
4
12
16
8
20
24
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
28
0
2
2.5
4
5
6
3.5
4.5
5.5
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
3
6.5
7
5V
6V
T
J
= 25°C
V
GS
= 10 V
7V
8V
4
3.5
3
2.5
2
1.5
1
0.5
T
J
= − 55°C
V
DS
≥
10 V
100°C
25°C
Figure 1. On−Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
10
8
6
V
GS
= 10 V
T
J
= 100°C
6
5.75
5.5
5.25
5
4.75
15 V
4.5
4.25
4
0
0.5
1
2
3
1.5
2.5
I
D
, DRAIN CURRENT (AMPS)
3.5
4
V
GS
= 10 V
T
J
= 25°C
25°C
4
− 55°C
2
0
0
0.5
1
2
2.5
1.5
3
I
D
, DRAIN CURRENT (AMPS)
3.5
4
Figure 3. On−Resistance versus Drain Current
and Temperature
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
RDS(on), DRAIN-TO-SOURCE RESISTANCE
(NORMALIZED)
2
V
GS
= 10 V
I
D
= 1 A
1.5
1000
V
GS
= 0 V
T
J
= 125°C
I DSS , LEAKAGE (nA)
100
100°C
1
10
25°C
0.5
− 50
− 25
0
25
50
75
100
125
150
1
0
50
100
150
200
250
300
350
400
450
500
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−To−Source Leakage
Current versus Voltage
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3
MTB2P50E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
1800
1600
1400
C, CAPACITANCE (pF)
1200
1000
800
600
400
200
0
10
5
V
GS
0
V
DS
C
rss
5
C
oss
10
15
20
25
1
10
100
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
C
rss
C
iss
V
DS
= 0 V
C
iss
C, CAPACITANCE (pF)
100
C
oss
10
C
rss
V
GS
= 0 V
T
J
= 25°C
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring which
is common to both the drain and gate current paths, produces
a voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a
function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also complicates
the mathematics. And finally, MOSFETs have finite internal
gate resistance which effectively adds to the resistance of the
driving source, but the internal resistance is difficult to
measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
1000
V
GS
= 0 V
T
J
= 25°C
C
iss
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 7a. Capacitance Variation
Figure 7b. High Voltage Capacitance
Variation
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4
MTB2P50E
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
12
Q
T
V
GS
8
Q
1
6
4
2
Q
3
0
0
2
4
6
8
10
12
14
V
DS
16
18
Q
T
, TOTAL CHARGE (nC)
Q
2
I
D
= 2 A
T
J
= 25°C
150
100
50
0
20
200
300
250
1000
V
DD
= 250 V
I
D
= 2 A
V
GS
= 10 V
T
J
= 25°C
t, TIME (ns)
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
100
t
f
t
d(off)
t
r
10
1
10
t
d(on)
100
R
G
, GATE RESISTANCE (OHMS)
Figure 8. Gate−To−Source and Drain−To−Source
Voltage versus Total Charge
Figure 9. Resistive Switching Time
Variation versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
2
V
GS
= 0 V
T
J
= 25°C
IS , SOURCE CURRENT (AMPS)
1.6
1.2
0.8
0.4
0
0.6
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed
in
AN569,
“Transient
Thermal
Resistance−General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded and the
transition time (t
r
,t
f
) do not exceed 10
ms.
In addition the total
power averaged over a complete switching cycle must not
exceed (T
J(MAX)
− T
C
)/(R
qJC
).
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 12). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
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