MMSF7P03HD
Preferred Device
Power MOSFET
7 A, 30 V, P−Channel SO−8
These miniature surface mount devices are designed for use in low
voltage, high speed switching applications where power efficiency is
important. Typical applications are DC−DC converters, and power
management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be
used for low voltage motor controls in mass storage products such as
disk drives and tape drives.
Features
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7 A, 30 V − R
DS(on)
= 35 mW
D
P−Channel
•
•
•
•
•
•
•
•
Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive − Can Be Driven by Logic ICs
Miniature SO−8 Surface Mount Package − Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, With Soft Recovery
I
DSS
Specified at Elevated Temperature
Mounting Information for SO−8 Package Provided
Pb−Free Package is Available
8
G
S
MARKING
DIAGRAM
8
SO−8
CASE 751
STYLE 12
1
S7P03
AYWWG
G
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage
Drain Current
Continuous
Symbol
V
DSS
V
GS
I
D
I
DM
I
S
P
D
T
J
, T
stg
E
AS
Value
30
±
20
7.0
50
2.3
2.5
− 55 to 150
500
Unit
Vdc
Vdc
Adc
Apk
Adc
W
°C
mJ
1
Continuous @ T
A
= 25°C
Single Pulse (t
p
≤
10
ms)
Source Current − Continuous @ T
A
= 25°C
Total Power Dissipation @ T
A
= 25°C
(Note 1)
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy − Starting T
J
= 25°C
(V
DD
= 30 Vdc, V
GS
= 5.0 Vdc,
V
DS
= 32 Vdc, I
L
= 10 Apk,
L = 10 mH, R
G
= 25
W)
Thermal Resistance, Junction−to−Ambient
Maximum Temperature for Soldering
S7P03 = Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
PIN ASSIGNMENT
Source
Source
Source
Gate
1
2
3
4
8
7
6
5
Drain
Drain
Drain
Drain
R
qJA
T
50
260
°C/W
°C
Top View
ORDERING INFORMATION
Device
MMSF7P03HDR2
MMSF7P03HDR2G
Package
SO−8
Shipping
†
2500 / Tape&Reel
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
1. When mounted on 1 in square FR−4 or G−10 (V
GS
= 10 V @ 10 seconds)
SO−8
2500 / Tape&Reel
(Pb−Free)
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
Preferred
devices are recommended choices for future use
and best overall value.
©
Semiconductor Components Industries, LLC, 2006
1
February, 2006 − Rev. 7
Publication Order Number:
MMSF7P03HD/D
MMSF7P03HD
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted) (Note 2)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 0.25 mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 30 Vdc, V
GS
= 0 Vdc)
(V
DS
= 30 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0 Vdc)
ON CHARACTERISTICS
(Note 3)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 0.25 mAdc)
Threshold Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 5.3 Adc)
(V
GS
= 4.5 Vdc, I
D
= 2.0 Adc)
Forward Transconductance (V
DS
= 15 Vdc, I
D
= 2.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 4)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(See Figure 8)
(V
DS
= 10 Vdc, I
D
= 4.9 Adc,
V
GS
= 6.0 Vdc)
(V
DD
= 15 Vdc, I
D
= 1.0 Adc,
V
GS
= 10 Vdc, R
G
= 6.0
W)
(V
DD
= 15 Vdc, I
D
= 1.0 Adc,
V
GS
= 4.5 Vdc, R
G
= 10
W)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I
S
= 2.3 Adc, V
GS
= 0 Vdc)
(I
S
= 2.3 Adc, V
GS
= 0 Vdc,
T
J
= 125°C)
V
SD
−
−
−
−
−
−
0.76
0.61
47.9
27
21
0.052
1.2
−
−
−
−
−
mC
Vdc
−
−
−
−
−
−
−
−
−
−
−
−
23.5
42.7
57.4
53.6
16
15.2
99.7
55.2
37.9
4.2
11.5
7.6
47
85.4
114.8
107.2
32
30.6
199.4
110.4
75.8
−
−
−
nC
ns
(V
DS
= 24 Vdc, V
GS
= 0 V,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
1200
580
160
1680
810
220
pF
V
GS(th)
1.0
R
DS(on)
−
−
g
FS
−
26
42
12
35
50
−
Mhos
−
−
mW
Vdc
V
(BR)DSS
30
I
DSS
−
−
I
GSS
−
−
−
−
1.0
25
100
nAdc
−
−
mAdc
Vdc
Symbol
Min
Typ
Max
Unit
Reverse Recovery Time
(I
S
= 4.9 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
Reverse Recovery Stored Charge
2. Negative sign for P−Channel device omitted for clarity.
3. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
4. Switching characteristics are independent of operating junction temperature.
t
rr
t
a
t
b
Q
RR
ns
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2
MMSF7P03HD
TYPICAL ELECTRICAL CHARACTERISTICS
12
I D, DRAIN CURRENT (AMPS)
10 V
6.0 V
10
4.5 V
8.0
6.0
4.0
2.0
0
0
RDS(on) DRAIN−TO−SOURCE RESISTANCE (OHMS)
,
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
RDS(on) DRAIN−TO−SOURCE RESISTANCE (OHMS)
,
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
4.3 V
4.1 V
12
3.7 V
3.5 V
I D, DRAIN CURRENT (AMPS)
T
J
= 25°C
10
8.0
6.0
4.0
2.0
T
J
= − 55°C
0
1.5
2.0
2.5
3.0
3.5
4.0
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
25°C
100°C
V
DS
. 10 V
3.9 V
V
GS
= 3.3 V
3.1 V
2.9 V
2.7 V
2.5 V
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.30
0.25
0.20
0.15
0.10
0.05
0
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
10
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
T
J
= 25°C
I
D
= 7.0 A
0.050
T
J
= 25°C
0.045
0.040
0.035
0.030
0.025
0.020
1.0
V
GS
= 4.5 V
10 V
2.0
3.0
4.0
5.0
6.0
7.0
8.0
9.0
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
RDS(on) DRAIN−TO−SOURCE RESISTANCE
,
(NORMALIZED)
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1.6
1.4
V
GS
= 10 V
I DSS LEAKAGE (nA)
,
1000
V
GS
= 0 V
T
J
= 125°C
100
1.2
1.0
0.8
0.6
100°C
10
0.4
0.2
0
−50
−25
0
25
50
75
100
125
150
T
J
, JUNCTION TEMPERATURE (°C)
1.0
0
5.0
10
15
20
25
30
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage
Current versus Voltage
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MMSF7P03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
− V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
− V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
3500
C, CAPACITANCE (pF)
3000
2500
2000
1500
1000
C
oss
500
0
−10
V
GS
0 V
DS
10
20
C
rss
30
C
iss
T
J
= 25°C
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
VGS GATE−TO−SOURCE VOLTAGE (VOLTS)
,
7.0
QT
6.0
30
5.0
Q1
Q2
V
GS
4.0
20
3.0
10
T
J
= 25°C
I
D
= 7.0 A
0
20
25
30
35
40
2.0
Q3
0
5.0
10
1.0
0
V
D
15
S
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Q
G
, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
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4
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
MMSF7P03HD
100
0
T
J
= 25°C
I
D
= 7.0 A
V
DD
= 15 V
V
GS
= 10 V
t
d(off)
t, TIME (ns)
100
t
f
t
r
10
t
d(on)
1.0
1.0
10
R
G
, GATE RESISTANCE (W)
100
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
DRAIN−TO−SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode
are very important in systems using it as a freewheeling or
commutating diode. Of particular interest are the reverse
recovery characteristics which play a major role in
determining switching losses, radiated noise, EMI and RFI.
System switching losses are largely due to the nature of
the body diode itself. The body diode is a minority carrier
device, therefore it has a finite reverse recovery time, t
rr
, due
to the storage of minority carrier charge, Q
RR
, as shown in
the typical reverse recovery wave form of Figure 11. It is this
stored charge that, when cleared from the diode, passes
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery
further increases switching losses. Therefore, one would
like a diode with short t
rr
and low Q
RR
specifications to
minimize these losses.
The abruptness of diode reverse recovery effects the
amount of radiated noise, voltage spikes, and current
ringing. The mechanisms at work are finite irremovable
circuit parasitic inductances and capacitances acted upon by
6.0
IS, SOURCE CURRENT (AMPS)
di/dt = 300 A/ms
5.0
4.0
3.0
2.0
1.0
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
t, TIME
T
J
= 25°C
V
GS
= 0 V
I
S
, SOURCE CURRENT
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
high di/dts. The diode’s negative di/dt during t
a
is directly
controlled by the device clearing the stored charge.
However, the positive di/dt during t
b
is an uncontrollable
diode characteristic and is usually the culprit that induces
current ringing. Therefore, when comparing diodes, the
ratio of t
b
/t
a
serves as a good indicator of recovery
abruptness and thus gives a comparative estimate of
probable noise generated. A ratio of 1 is considered ideal and
values less than 0.5 are considered snappy.
Compared to ON Semiconductor standard cell density
low voltage MOSFETs, high cell density MOSFET diodes
are faster (shorter t
rr
), have less stored charge and a softer
reverse recovery characteristic. The softness advantage of
the high cell density diode means they can be forced through
reverse recovery at a higher di/dt than a standard cell
MOSFET diode without increasing the current ringing or the
noise generated. In addition, power dissipation incurred
from switching the diode will be less due to the shorter
recovery time and lower switching losses.
Figure 10. Diode Forward Voltage versus Current
Figure 11. Reverse Recovery Time (t
rr
)
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