MMDF2P02E
Power MOSFET
2 Amps, 25 Volts
P−Channel SO−8, Dual
These miniature surface mount MOSFETs feature ultra low R
DS(on)
and true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
drain−to−source diode has a low reverse recovery time. These devices
are designed for use in low voltage, high speed switching applications
where power efficiency is important. Typical applications are dc−dc
converters, and power management in portable and battery powered
products such as computers, printers, cellular and cordless phones.
They can also be used for low voltage motor controls in mass storage
products such as disk drives and tape drives. The avalanche energy is
specified to eliminate the guesswork in designs where inductive loads
are switched and offer additional safety margin against unexpected
voltage transients.
Features
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2 AMPERES, 25 VOLTS
R
DS(on)
= 250 mW
P−Channel
D
G
S
•
•
•
•
•
•
•
•
•
Ultra Low R
DS(on)
Provides Higher Efficiency and Extends Battery Life
Logic Level Gate Drive
−
Can Be Driven by Logic ICs
Miniature SO−8 Surface Mount Package
−
Saves Board Space
Diode Is Characterized for Use In Bridge Circuits
Diode Exhibits High Speed, with Soft Recovery
I
DSS
Specified at Elevated Temperatures
Avalanche Energy Specified
Mounting Information for SO−8 Package Provided
This is a Pb−Free Device
Rating
Symbol
V
DSS
V
GS
I
D
I
D
Value
25
±
20
2.5
1.7
13
2.0
16
−55
to 150
245
Unit
Vdc
Vdc
Adc
Apk
W
mW/°C
°C
mJ
MARKING
DIAGRAM
8
8
1
SO−8, Dual
CASE 751
STYLE 11
1
F2P02 = Specific Device Code
A
= Assembly Location
Y
= Year
WW
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
F2PO2
AYWW
G
G
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted) (Note 1)
Drain−to−Source Voltage
Gate−to−Source Voltage
−
Continuous
Drain Current
−
Continuous @ T
A
= 25°C
Drain Current
−
Continuous @ T
A
= 100°C
Drain Current
−
Single Pulse (t
p
≤
10
ms)
Total Power Dissipation @ T
A
= 25°C
(Note 2)
Derate above 25°C
Operating and Storage Temperature Range
Single Pulse Drain−to−Source Avalanche
Energy
−
Starting T
J
= 25°C
(V
DD
= 20 Vdc, V
GS
= 10 Vdc, Peak
I
L
= 7.0 Apk, L = 10 mH, R
G
= 25
W)
Thermal Resistance, Junction−to−Ambient
(Note 2)
Maximum Lead Temperature for Soldering
Purposes, 0.0625″ from case for 10 sec.
I
DM
P
D
PIN ASSIGNMENT
Source−1
Gate−1
Source−2
Gate−2
1
2
3
4
8
7
6
5
Drain−1
Drain−1
Drain−2
Drain−2
T
J
, T
stg
E
AS
Top View
°C/W
°C
R
qJA
T
L
62.5
260
ORDERING INFORMATION
Device
MMDF2P02ER2G
Package
SO−8
(Pb−Free)
Shipping
†
2500 Tape & Reel
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Negative sign for P−Channel device omitted for clarity.
2. Mounted on 2″ square FR4 board (1″ sq. 2 oz. Cu 0.06″ thick single sided) with
one die operating, 10 sec. max.
©
Semiconductor Components Industries, LLC, 2011
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.
October, 2011
−
Rev. 9
1
Publication Order Number:
MMDF2P02E/D
MMDF2P02E
ELECTRICAL CHARACTERISTICS
(T
A
= 25°C unless otherwise noted) (Note 3)
Characteristic
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
(V
GS
= 0 Vdc, I
D
= 250
mAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(V
DS
= 20 Vdc, V
GS
= 0 Vdc)
(V
DS
= 20 Vdc, V
GS
= 0 Vdc, T
J
= 125°C)
Gate−Body Leakage Current (V
GS
=
±
20 Vdc, V
DS
= 0)
ON CHARACTERISTICS
(Note 4)
Gate Threshold Voltage
(V
DS
= V
GS
, I
D
= 250
mAdc)
Temperature Coefficient (Negative)
Static Drain−to−Source On−Resistance
(V
GS
= 10 Vdc, I
D
= 2.0 Adc)
(V
GS
= 4.5 Vdc, I
D
= 1.0 Adc)
Forward Transconductance (V
DS
= 3.0 Vdc, I
D
= 1.0 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS
(Note 5)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Gate Charge
(V
DS
= 16 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc)
(V
DD
= 10 Vdc, I
D
= 2.0 Adc,
V
GS
= 10 Vdc, R
G
= 6.0
W)
(V
DD
= 10 Vdc, I
D
= 2.0 Adc,
V
GS
= 5.0 Vdc, R
G
= 6.0
W)
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
Q
T
Q
1
Q
2
Q
3
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage (Note 4)
Reverse Recovery Time
See Figure 11
(I
S
= 2.0 Adc, V
GS
= 0 Vdc)
V
SD
t
rr
(I
S
= 2.0 Adc, V
GS
= 0 Vdc,
dI
S
/dt = 100 A/ms)
t
a
t
b
Q
RR
−
−
−
−
−
1.5
32
19
12
0.035
2.0
64
−
−
−
mC
Vdc
ns
−
−
−
−
−
−
−
−
−
−
−
−
20
40
53
41
13
29
30
28
10
1.0
3.5
3.0
40
80
106
82
26
58
60
56
15
−
−
−
nC
ns
(V
DS
= 16 Vdc, V
GS
= 0 Vdc,
f = 1.0 MHz)
C
iss
C
oss
C
rss
−
−
−
340
220
75
475
300
150
pF
V
GS(th)
1.0
−
−
−
1.0
2.0
3.8
0.19
0.3
2.8
3.0
−
0.25
0.4
−
Vdc
V
(BR)DSS
25
−
−
−
−
−
2.2
−
−
−
−
−
1.0
10
100
Vdc
mV/°C
mAdc
Symbol
Min
Typ
Max
Unit
I
DSS
I
GSS
nAdc
R
DS(on)
W
g
FS
Mhos
Reverse Recovery Storage Charge
3. Negative sign for P−Channel device omitted for clarity.
4. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
5. Switching characteristics are independent of operating junction temperature.
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MMDF2P02E
TYPICAL ELECTRICAL CHARACTERISTICS
4
V
GS
= 10 7 V
I D , DRAIN CURRENT (AMPS)
3
4.3 V
2
4.1 V
3.9 V
1
3.7 V
3.5 V
3.3 V
0
0.4
0.8
1.2
1.6
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
2
5V
4.7 V
4.5 V
T
J
= 25°C
I D , DRAIN CURRENT (AMPS)
3
100°C
2
25°C
T
J
= -55°C
1
4
V
DS
≥
10 V
0
0
2.5
3
3.5
4
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
4.5
Figure 1. On−Region Characteristics
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
0.6
0.5
0.4
0.3
0.2
0.1
0
3
4
5
6
7
8
9
10
V
GS
, GATE-TO-SOURCE VOLTAGE (VOLTS)
I
D
= 1 A
T
J
= 25°C
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
0.6
Figure 2. Transfer Characteristics
T
J
= 25°C
0.5
0.4
V
GS
= 4.5
0.3
0.2
10 V
0.1
0
0.5
1
I
D
, DRAIN CURRENT (AMPS)
1.5
2
Figure 3. On−Resistance versus
Gate−to−Source Voltage
RDS(on) , DRAIN-TO-SOURCE RESISTANCE (NORMALIZED)
2.0
V
GS
= 10 V
I
D
= 2 A
1.5
I DSS , LEAKAGE (nA)
100
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
V
GS
= 0 V
T
J
= 125°C
10
1.0
0.5
100°C
0
- 50
- 25
0
25
50
75
100
125
150
1
0
4
8
12
16
20
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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MMDF2P02E
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
G(AV)
) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V
GS
remains virtually constant at a level
known as the plateau voltage, V
SGP
. Therefore, rise and fall
times may be approximated by the following:
t
r
= Q
2
x R
G
/(V
GG
−
V
GSP
)
t
f
= Q
2
x R
G
/V
GSP
where
V
GG
= the gate drive voltage, which varies from zero to V
GG
R
G
= the gate drive resistance
and Q
2
and V
GSP
are read from the gate charge curve.
V
DS
= 0 V
C
iss
V
GS
= 0 V
T
J
= 25°C
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)
1000
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
d(on)
= R
G
C
iss
In [V
GG
/(V
GG
−
V
GSP
)]
t
d(off)
= R
G
C
iss
In (V
GG
/V
GSP
)
The capacitance (C
iss
) is read from the capacitance curve at
a voltage corresponding to the off−state condition when
calculating t
d(on)
and is read at a voltage corresponding to the
on−state when calculating t
d(off)
.
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
12
QT
9
V
DS
6
Q1
Q2
V
GS
16
800
C, CAPACITANCE (pF)
12
600
8
400
C
rss
C
iss
C
oss
C
rss
200
0
10
3
Q3
4
I
D
= 2 A
T
J
= 25°C
2
4
6
8
Q
g
, TOTAL GATE CHARGE (nC)
10
0
12
5
V
GS
0
V
DS
5
10
15
20
25
30
0
0
GATE-TO-SOURCE OR DRAIN-TO-SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
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VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
MMDF2P02E
100
V
DD
= 10 V
I
D
= 2 A
V
GS
= 10 V
T
J
= 25°C
t, TIME (ns)
2
T
J
= 25°C
VGS = 0 V
IS, SOURCE CURRENT (AMPS)
100
1.6
1.2
t
d(off)
t
r
t
f
t
d(on)
10
1
10
R
G
, GATE RESISTANCE (OHMS)
0.8
0.4
0
0.6
0.8
1
1.2
1.4
V
SD
, SOURCE-TO-DRAIN VOLTAGE (VOLTS)
1.6
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage
versus Current
di/dt = 300 A/ms
I S , SOURCE CURRENT
Standard Cell Density
t
rr
High Cell Density
t
rr
t
b
t
a
t, TIME
Figure 11. Reverse Recovery Time (t
rr
)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
C
) of 25°C.
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance
−
General Data and Its Use.”
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
(I
DM
) nor rated voltage (V
DSS
) is exceeded, and that the
transition time (t
r
, t
f
) does not exceed 10
ms.
In addition the
total power averaged over a complete switching cycle must
not exceed (T
J(MAX)
−
T
C
)/(R
qJC
).
This MOSFET can be safely used in switching circuits
with unclamped inductive loads. For reliable operation, the
stored energy from circuit inductance dissipated in the
transistor while in avalanche must be less than the rated limit
and must be adjusted for operating conditions differing from
those specified. Although industry practice is to rate in terms
of energy, avalanche energy capability is not a constant. The
energy rating decreases non−linearly with an increase of
peak current in avalanche and peak junction temperature.
Although many MOSFETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
current (I
DM
), the energy rating is specified at rated
continuous current (I
D
), in accordance with industry
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I
D
can safely be
assumed to equal the values indicated.
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