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SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
D
Member of the Texas Instruments
D
D
D
D
D
Widebus
Family
EPIC
(Enhanced-Performance Implanted
CMOS) Submicron Process
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DGG OR DL PACKAGE
(TOP VIEW)
description
This 18-bit bus transceiver is designed for 1.65-V
to 3.6-V V
CC
operation.
The SN74ALVCH16863 is an 18-bit noninverting
transceiver
designed
for
synchronous
communication between data buses. The
control-function
implementation
minimizes
external timing requirements.
The SN74ALVCH16863 can be used as two 9-bit
transceivers or one 18-bit transceiver. They allow
data transmission from the A bus to the B bus or
from the B bus to the A bus, depending on the logic
level at the output-enable (OEAB or OEBA)
inputs.
1OEAB
1B1
1B2
GND
1B3
1B4
V
CC
1B5
1B6
1B7
GND
1B8
1B9
GND
GND
2B1
2B2
GND
2B3
2B4
2B5
V
CC
2B6
2B7
GND
2B8
2B9
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1A1
1A2
GND
1A3
1A4
V
CC
1A5
1A6
1A7
GND
1A8
1A9
GND
GND
2A1
2A2
GND
2A3
2A4
2A5
V
CC
2A6
2A7
GND
2A8
2A9
2OEBA
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN74ALVCH16863 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each 9-bit section)
INPUTS
OPERATION
OEAB
H
L
H
OEBA
L
H
H
B data to A bus
A data to B bus
Isolation
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1999, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3–415
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
logic symbol
†
56
1OEBA
1OEAB
2OEBA
2OEAB
1A1
28
55
1
29
EN1
EN2
EN3
EN4
1
1
1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
1A9
2A1
54
52
51
49
48
47
45
44
41
3
1
1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2A9
40
38
37
36
34
33
31
30
4
17
19
20
21
23
24
26
27
2B2
2B3
2B4
2B5
2B6
2B7
2B8
2B9
2
3
5
6
8
9
10
12
13
16
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1B9
2B1
2
1B1
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1OEBA
1OEAB
56
1
2OEAB
2OEBA
29
28
55
1A1
2
1B1
2A1
41
16
2B1
To Eight Other Channels
To Eight Other Channels
3–416
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
Input voltage range, V
I
: Except I/O ports (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I/O ports (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Output clamp current, I
OK
(V
O
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
Continuous output current, I
O
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through each V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±100
mA
Package thermal impedance,
θ
JA
(see Note 3): DGG package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81°C/W
DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 4)
MIN
VCC
VIH
Supply voltage
High-level input voltage
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VIL
VI
VO
Low-level input voltage
Input voltage
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
1.65
0.65
×
VCC
1.7
2
0.35
×
VCC
0.7
0.8
VCC
VCC
–4
–12
–12
–24
4
12
12
24
10
ns/V
mA
mA
V
V
V
V
MAX
3.6
UNIT
V
IOH
High-level output current
IOL
Low-level output current
∆t/∆v
Input transition rise or fall rate
TA
Operating free-air temperature
–40
85
°C
NOTE 4: All unused control inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3–417
SN74ALVCH16863
18-BIT TRANSCEIVER
WITH 3-STATE OUTPUTS
SCES060B – DECEMBER 1995 – REVISED FEBRUARY 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
IOH = –100
µA
IOH = –4 mA
IOH = –6 mA
VOH
IOH = –12 mA
IOH = –24 mA
IOL = 100
µA
IOL = 4 mA
IOL = 6 mA
IOL = 12 mA
IOL = 24 mA
VI = VCC or GND
VI = 0.58 V
VI = 1.07 V
II(hold)
VI = 0.7 V
VI = 1.7 V
VI = 0.8 V
VI = 2 V
IOZ
ICC
∆I
CC
Ci
Co
Control inputs
Data inputs
Outputs
VI = 0 to 3.6 V‡
VO = VCC or GND
VI = VCC or GND,
One input at VCC – 0.6 V,
VI = VCC or GND
IO = 0
Other inputs at VCC or GND
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3V
1.65 V to 3.6 V
1.65 V
2.3 V
2.3 V
2.7 V
3V
3.6 V
1.65 V
1.65 V
2.3 V
2.3 V
3V
3V
3.6 V
3.6 V
3.6 V
3 V to 3.6 V
3.3 V
3.5
6
25
–25
45
–45
75
–75
±500
±10
40
750
µA
µA
µA
pF
µA
MIN
TYP†
MAX
UNIT
VCC–0.2
1.2
2
1.7
2.2
2.4
2
0.2
0.45
0.4
0.7
0.4
0.55
±5
µA
V
V
VOL
II
VO = VCC or GND
3.3 V
7.5
pF
† All typical values are at VCC = 3.3 V, TA = 25°C.
‡ This is the bus-hold maximum dynamic current. It is the minimum overdrive current required to switch the input from one state to another.
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 1 through 3)
PARAMETER
tpd
ten
tdis
FROM
(INPUT)
A or B
OEAB or OEBA
OEAB or OEBA
TO
(OUTPUT)
B or A
A or B
A or B
VCC = 1.8 V
TYP
§
§
§
VCC = 2.5 V
±
0.2 V
MIN
1
1
1.3
MAX
4.1
5.7
5.5
VCC = 2.7 V
MIN
MAX
4
5.8
4.7
VCC = 3.3 V
±
0.3 V
MIN
1
1
1.4
MAX
3.4
4.7
4.2
ns
ns
ns
UNIT
§ This information was not available at the time of publication.
3–418
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