Document Revision History
Version History
Rev 1.0
Rev 2.0
Initial Public Release
Added Package Pins to GPIO Table in
Part 8 General Purpose Input/Output (GPIO).
Added
“Typical Min” values to
Table 10-18.
Editing grammar, spelling, consistency of language
throughout family. Updated values in Regulator Parameters
Table 10-9,
External Clock
Operation Timing Requirements
Table 10-13,
SPI Timing
Table 10-18,
ADC Parameters
Table 10-24,
and IO Loading Coefficients at 10MHz
Table 10-25.
Added
Part 4.8,
added the word “access” to FM Error Interrupt in
Table 4-5,
documenting only
Typ. numbers for LVI in
Table 10-6,
updated EMI numbers and writeup in
Part 10.8.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data, Corrected typo in
Table 10-3
in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Memory Module; corrected thermal
numbers for 144 LQFP in
Table 10-3;
removed unneccessary notes in
Table 10-12;
corrected
temperature range in
Table 10-14;
added ADC calibration information to
Table 10-24
and new
graphs in
Figure 10-22
Adding/clarifing notes to
Table 4-4
to help clarify independent program flash blocks and other
Program Flash modes, clarification to
Table 10-23,
corrected Digital Input Current Low (pull-up
enabled) numbers in
Table 10-5.
Removed text and Table 10-2; replaced with note to
Table 10-1.
Added 56F8156 information; edited to indicate differences in 56F8356 and 56F8156. Refor-
matted for Freescale look and feel. Updated Temperature Sensor and ADC tables, then
updated balance of electrical tables for consistency throughout family. Clarified I/O power
description in
Table 2-2,
added note to
Table 10-7
and clarified
Section 12.3.
Added output voltage maximum value and note to clarify in
Table 10-1;
also removed overall
life expectancy note, since life expectancy is dependent on customer usage and must be
determined by reliability engineering. Clarified value and unit measure for Maximum allowed
P
D
in
Table 10-3.
Corrected note about average value for Flash Data Retention in
Table 10-4.
Added new RoHS-compliant orderable part numbers in
Table 13-1.
Updated
Table 10-24
to reflect new value for maximum Uncalibrated Gain Error
Deleted RSTO from Pin Group 2 (listed after
Table 10-1).
Deleted formula for Max Ambient
Operating Temperature (Automotive) and Max Ambient Operating Temperature (Industrial) in
Table 10-4.
Added RoHS-compliance and “pb-free” language to back cover.
Added information/corrected state during reset in
Table 2-2.
Clarified external reference crys-
tal frequency for PLL in
Table 10-14
by increasing maximum value to 8.4MHz..
Replaced “Tri-stated” with an explanation in State During Reset column in
Table 2-2.
• Added the following note to the description of the TMS signal in
Table 2-2:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Added the following note to the description of the TRST signal in
Table 2-2:
Note:
For normal operation, connect TRST directly to V
SS
. If the design is to be used in a debugging
environment, TRST may be tied to V
SS
through a 1K resistor.
Description of Change
Rev 3.0
Rev 4.0
Rev 5.0
Rev 6.0
Rev 7.0
Rev 8.0
Rev 9.0
Rev 10.0
Rev 11.0
Rev 12.0
Rev. 13
Please see http://www.freescale.com for the most current data sheet revision.
56F8356 Technical Data, Rev. 13
2
Freescale Semiconductor
Preliminary
56F8356/56F8156 General Description
Note:
Features in italics are NOT available in the 56F8156 device.
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data memory
• Chip Select Logic for glueless interface to ROM and
SRAM
• 256KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 16KB of Data RAM
• 16KB of Boot Flash
• Up to two 6-channel PWM modules
• Four 4-channel, 12-bit ADCs
OCR_DIS
V
DD
V
ss
7
5
• Temperature Sensor
• Up to two Quadrature Decoders
• Optional on-chip regulator
• FlexCAN module
• Two Serial Communication Interfaces (SCIs)
• Up to two Serial Peripheral Interfaces (SPIs)
• Up to four general-purpose Quad Timers
• Computer Operating Properly (COP) / Watchdog
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package
RSTO
EMI_MODE
EXTBOOT
5
V
PP
2
V
CAP
4
V
DDA
2
V
SSA
RESET
6
3
3
6
3
4
4
4
5
4
4
PWM Outputs
Current Sense Inputs
or
GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
PWMA
JTAG/
EOnCE
Port
Digital Reg
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
R/W Control
XDB2
XAB1
XAB2
PAB
6
External
Address Bus
Switch
2
8
Memory
ADCB
Program Memory
128K x 16 Flash
2K x 16 RAM
8K x 16
Boot
Flash
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
AD1
TEMP_SENSE
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
External Bus
Interface Unit
4
Data Memory
4K x 16 Flash
8K x 16 RAM
PDB
CDBR
CDBW
System Bus
Control
7
External Data
Bus Switch
9
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
4
IPBus Bridge (IPBB)
Decoding
Peripherals
Clock
resets
Bus Control
2
GPIOD0-1 or CS2-3
PS or CS0 or GPIOD8
DS or CS1 or GPIOD9
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
1
2
2
PLL
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
P
System
O
Integration
R
Module
O
Clock
S
Generator
C
XTAL
EXTAL
IRQA IRQB
CLKO CLKMODE
56F8356 / 56F8156 Block Diagram
56F8356 Technical Data, Rev. 13
Freescale Semiconductor
Preliminary
3
Table of Contents
Part 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1
1.2
1.3
1.4
1.5
1.6
56F8356/56F8156 Features . . . . . . . . . . . .5
Device Description. . . . . . . . . . . . . . . . . . . .7
Award-Winning Development
Environment . . . . . . . . . . . . . . . . . . . .9
Architecture Block Diagram . . . . . . . . . . . .10
Product Documentation . . . . . . . . . . . . . . .14
Data Sheet Conventions . . . . . . . . . . . . . .14
7.2
Flash Access Blocking Mechanisms . . . . 127
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.1
8.2
8.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . 130
Memory Maps . . . . . . . . . . . . . . . . . . . . . 130
Configuration. . . . . . . . . . . . . . . . . . . . . . 130
Part 9 Joint Test Action Group (JTAG) . . 136
Part 2 Signal/Connection Descriptions . . . . 15
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . .15
Signal Pins. . . . . . . . . . . . . . . . . . . . . . . . .18
9.1
56F8356 Information . . . . . . . . . . . . . . . . 136
Part 10 Specifications . . . . . . . . . . . . . . . . 136
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
General Characteristics. . . . . . . . . . . . . . 136
DC Electrical Characteristics. . . . . . . . . . 140
AC Electrical Characteristics . . . . . . . . . . 145
Flash Memory Characteristics. . . . . . . . . 145
External Clock Operation Timing . . . . . . 146
Phase Locked Loop Timing. . . . . . . . . . . 146
Crystal Oscillator Timing . . . . . . . . . . . . . 147
External Memory Interface Timing . . . . . 147
Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . . 150
Serial Peripheral Interface (SPI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 153
Quad Timer Timing . . . . . . . . . . . . . . . . . 157
Quadrature Decoder Timing . . . . . . . . . . 158
Serial Communication Interface (SCI)
Timing. . . . . . . . . . . . . . . . . . . . . . . 159
Controller Area Network (CAN) Timing . . 159
JTAG Timing . . . . . . . . . . . . . . . . . . . . . . 160
Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . . . 161
Equivalent Circuit for ADC Inputs . . . . . . 164
Power Consumption . . . . . . . . . . . . . . . . 165
Part 3 On-Chip Clock Synthesis (OCCS) . . . 38
3.1
3.2
3.3
Introduction . . . . . . . . . . . . . . . . . . . . . . . .38
External Clock Operation. . . . . . . . . . . . . .38
Registers . . . . . . . . . . . . . . . . . . . . . . . . . .40
Part 4 Memory Map . . . . . . . . . . . . . . . . . . . . 40
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . .40
Program Map . . . . . . . . . . . . . . . . . . . . . . .42
Interrupt Vector Table . . . . . . . . . . . . . . . .43
Data Map . . . . . . . . . . . . . . . . . . . . . . . . . .47
Flash Memory Map . . . . . . . . . . . . . . . . . .47
EOnCE Memory Map. . . . . . . . . . . . . . . . .49
Peripheral Memory Mapped Registers . . .50
Factory Programmed Memory . . . . . . . . . .77
Part 5 Interrupt Controller (ITCN) . . . . . . . . . 77
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . .77
Features. . . . . . . . . . . . . . . . . . . . . . . . . . .77
Functional Description . . . . . . . . . . . . . . . .78
Block Diagram . . . . . . . . . . . . . . . . . . . . . .80
Operating Modes . . . . . . . . . . . . . . . . . . . .80
Register Descriptions. . . . . . . . . . . . . . . . .80
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .108
Part 11 Packaging . . . . . . . . . . . . . . . . . . . 167
11.1
11.2
56F8356 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 167
56F8156 Package and Pin-Out
Information . . . . . . . . . . . . . . . . . . . 169
Part 6 System Integration Module (SIM) . . 109
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
Overview . . . . . . . . . . . . . . . . . . . . . . . . .109
Features. . . . . . . . . . . . . . . . . . . . . . . . . .109
Operating Modes . . . . . . . . . . . . . . . . . . .110
Operating Mode Register. . . . . . . . . . . . .110
Register Descriptions. . . . . . . . . . . . . . . .111
Clock Generation Overview . . . . . . . . . . .125
Power-Down Modes Overview . . . . . . . .125
Stop and Wait Mode Disable Function . .126
Resets . . . . . . . . . . . . . . . . . . . . . . . . . . .126
Part 12 Design Considerations . . . . . . . . . 174
12.1
12.2
12.3
Thermal Design Considerations . . . . . . . 174
Electrical Design Considerations . . . . . . 175
Power Distribution and I/O Ring
Implementation . . . . . . . . . . . . . . . . 176
Part 13 Ordering Information . . . . . . . . . . 177
Part 7 Security Features . . . . . . . . . . . . . . . 127
7.1
Operation with Security Enabled . . . . . . .127
56F8356 Technical Data, Rev. 13
4
Freescale Semiconductor
Preliminary
56F8356/56F8156 Features
Part 1 Overview
1.1 56F8356/56F8156 Features
1.1.1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Core
Efficient 16-bit 56800E family controller engine with dual Harvard architecture
Up to 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
1.1.2
Differences Between Devices
Table 1-1
outlines the key differences between the 56F8356 and 56F8156 devices.
Table 1-1 Device Differences
Feature
Guaranteed Speed
Program RAM
Data Flash
PWM
CAN
Quad Timer
Quadrature Decoder
Temperature Sensor
Dedicated GPIO
56F8356
60MHz/60 MIPS
4KB
8KB
2x6
1
4
2x4
1
—
56F8156
40MHz/40 MIPS
Not Available
Not Available
1x6
Not Available
2
1x4
Not Available
5
56F8356 Technical Data, Rev. 13
Freescale Semiconductor
Preliminary
5
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