Document Revision History
Version History
Rev. 0
Rev. 1
Initial public release.
• In Table 10-4, added an entry for flash data retention with less than 100 program/erase
cycles (minimum 20 years).
• In Table 10-6, changed the device clock speed in STOP mode from 8MHz to 4MHz.
• In Table 10-12, changed the typical relaxation oscillator output frequency in Standby mode
from 400kHz to 200kHz.
• Changed input propagation delay values in Table 10-21 as follows:
Old values: 1
μs
typical, 2
μs
maximum
New values: 35 ns typical, 45 ns maximum
Rev. 2
Rev. 3
In Table 10-20, changed the maximum ADC internal clock frequency from 8MHz to 5.33MHz.
• Added the following note to the description of the TMS signal in Table 2-3:
Note:
Always tie the TMS pin to V
DD
through a 2.2K resistor.
• Changed the description of the GPIOC4 signal in Table 2-3 (was “...the
signal goes to both
the ANA0 and CMPAI3”,
is “...the
signal goes to both ANB0 and CMPB13”).
Rev. 4
• Changed the ITCN_BASE address In
Table 5-3
(was $00 F060, is $00 F0E0).
• In
Figure 5-10,
moved the footnote marker (superscript 1) from bit 4 to “RESET”.
• Changed the STANDBY > STOP I
DD
values in
Table 10-6
as follows:
Typical: was 290μA, is 540μA
Maximum: was 390μA, is 650μA
• Changed the POWERDOWN I
DD
values in
Table 10-6
as follows:
Typical: was 190μA, is 440μA
Maximum: was 250μA, is 550μA
• Changed footnote 1 in
Table 10-12
(was “Output frequency after application of 8MHz trim
value, at 125°C.”, is “Output frequency after application of factory trim”).
• Deleted the text “at 125°C” from
Figure 10-5.
• Changed the maximum input offset voltage in
Table 10-21
(was +/- 20 mV, is ±35 mV).
Rev. 5
• In
Table 2-3,
changed V
CAP
value from 4.7μF to 2.2μF.
• Revised
Section 7, Security Features.
• Added information for 56F8027 device throughout document.
• Fixed miscellaneous typos.
Description of Change
56F8037/56F8027 Data Sheet, Rev. 6
2
Freescale Semiconductor
56F8037/56F8027 General Description
• Up to 32 MIPS at 32MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• 56F8037 offers 64KB (32K x 16) Program Flash
• 56F8027 offers 32KB (16K x 16) Program Flash
• 56F8037 offers 8KB (4K x 16) Unified Data/Program
RAM
• 56F8027 offers 4KB (2K x 16) Unified Data/Program
RAM
• One 6-channel PWM module
• Two 8-channel 12-bit Analog-to-Digital Converters
(ADCs)
• Two 12-bit Digital-to-Analog Converters (DACs)
• Two Analog Comparators
RESET or
GPIOA
4
• Three Programmable Interval Timers (PITs)
• Two Queued Serial Communication Interfaces (QSCIs)
with LIN slave functionality
• Two Queued Serial Peripheral Interfaces (QSPIs)
• Freescale’s scalable controller area network (MSCAN)
2.0 A/B Module
• Two 16-bit Quad Timers
• One Inter-Integrated Circuit (I
2
C) port
• Computer Operating Properly (COP)/Watchdog
• On-Chip Relaxation Oscillator
• Integrated Power-On Reset (POR) and Low-Voltage
Interrupt (LVI) module
• JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
V
CAP
2
V
DD
3
V
SS
4
V
DDA
V
SSA
14
PWM
or TMRA or TMRB
or CMP or QSPI1
or GPIOA
Program Controller
and Hardware
Looping Unit
JTAG/EOnCE
Port or
GPIOD
Digital Reg
Analog Reg
16-Bit
56800E Core
Low-Voltage
Supervisor
Bit
Manipulation
Unit
Address
Generation Unit
2
DAC
or GPIOD
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
8
PAB
PDB
CDBR
CDBW
AD0
ADC
or CMP
or QSCI1
or GPIOC
AD1
Memory
Program Memory
32K x 16 Flash
16K x 16 Flash
Unified Data /
Program RAM
4K x 16
2K x 16
XDB2
XAB1
XAB2
PAB
PDB
CDBR
CDBW
R/W Control
8
System Bus
Control
Programmable
Interval
Timer
IPBus Bridge (IPBB)
I
2
C
or CAN
or TMRB
or CMP
or GPIOB
QSPI0
or PWM
or I
2
C
or TMRA
or GPIOB
QSCI0
or PWM
or I
2
C
or QSPI1
or TMRA
or TMRB
or GPIOB
4
COP/
Watchdog
Interrupt
Controller
System
Integration
Module
P
O
R
O
Clock
S
Generator*
C
XTAL, CLKIN, or
GPIOD
EXTAL or GPIOD
6
4
*Includes On-Chip
Relaxation Oscillator
56F8037/56F8027 Block Diagram
56F8037/56F8027 Data Sheet, Rev. 6
4
Freescale Semiconductor
56F8037/56F8027 Data Sheet Table of Contents
Part 1 Overview. . . . . . . . . . . . . . . . . . . . . . . . 6
1.1
1.2
1.3
1.4
1.5
1.6
56F8037/56F8027 Features . . . . . . . . . . . 6
56F8037/56F8027 Description . . . . . . . . . 8
Award-Winning Development
Environment . . . . . . . . . . . . . . . . . . . 9
Architecture Block Diagram . . . . . . . . . . . 9
Product Documentation . . . . . . . . . . . . . 18
Data Sheet Conventions . . . . . . . . . . . . . 18
7.3
Product Analysis. . . . . . . . . . . . . . . . . . 131
Part 8 General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . . . .131
8.1
8.2
8.3
Introduction. . . . . . . . . . . . . . . . . . . . . . 131
Configuration . . . . . . . . . . . . . . . . . . . . 131
Reset Values . . . . . . . . . . . . . . . . . . . . 135
Part 9 Joint Test Action Group (JTAG) . . .140
Part 2 Signal/Connection Descriptions . . . 19
2.1
2.2
Introduction . . . . . . . . . . . . . . . . . . . . . . . 19
56F8037/56F8027 Signal Pins . . . . . . . . 24
9.1
56F8037/56F8027 Information . . . . . . . 140
Part 10Specifications. . . . . . . . . . . . . . . . . .140
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
10.10
10.11
10.12
10.13
10.14
10.15
10.16
10.17
10.18
10.19
General Characteristics . . . . . . . . . . . . 140
DC Electrical Characteristics . . . . . . . . 144
AC Electrical Characteristics . . . . . . . . 147
Flash Memory Characteristics . . . . . . . 148
External Clock Operation Timing . . . . . 148
Phase Locked Loop Timing . . . . . . . . . 149
Relaxation Oscillator Timing. . . . . . . . . 149
Reset, Stop, Wait, Mode Select, and
Interrupt Timing . . . . . . . . . . . . . . 151
Serial Peripheral Interface (SPI) Timing 152
Quad Timer Timing. . . . . . . . . . . . . . . . 156
Queued Serial Communication Interface
(QSCI) Timing . . . . . . . . . . . . . . . 158
Freescale’s Scalable Controller Area
Network (MSCAN) Timing . . . . . . 159
Inter-Integrated Circuit Interface (I2C)
Timing . . . . . . . . . . . . . . . . . . . . . 159
JTAG Timing. . . . . . . . . . . . . . . . . . . . . 161
Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . . . . 162
Equivalent Circuit for ADC Inputs . . . . . 163
Comparator (CMP) Parameters . . . . . . 164
Digital-to-Analog Converter (DAC)
Parameters . . . . . . . . . . . . . . . . . 164
Power Consumption . . . . . . . . . . . . . . . 166
Part 3 OCCS . . . . . . . . . . . . . . . . . . . . . . . . . 40
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
Overview . . . . . . . . . . . . . . . . . . . . . . . . . 40
Features . . . . . . . . . . . . . . . . . . . . . . . . . 41
Operating Modes . . . . . . . . . . . . . . . . . . 41
Internal Clock Source . . . . . . . . . . . . . . . 42
Crystal Oscillator. . . . . . . . . . . . . . . . . . . 42
Ceramic Resonator . . . . . . . . . . . . . . . . . 43
External Clock Input - Crystal Oscillator
Option. . . . . . . . . . . . . . . . . . . . . . . 43
Alternate External Clock Input . . . . . . . . 44
Part 4 Memory Maps. . . . . . . . . . . . . . . . . . . 44
4.1
4.2
4.3
4.4
4.5
4.6
Introduction . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Vector Table . . . . . . . . . . . . . . . 45
Program Map . . . . . . . . . . . . . . . . . . . . . 47
Data Map . . . . . . . . . . . . . . . . . . . . . . . . 48
EOnCE Memory Map . . . . . . . . . . . . . . . 50
Peripheral Memory-Mapped Registers . . 51
Part 5 Interrupt Controller (ITCN) . . . . . . . . 68
5.1
5.2
5.3
5.4
5.5
5.6
5.7
Introduction . . . . . . . . . . . . . . . . . . . . . . . 68
Features . . . . . . . . . . . . . . . . . . . . . . . . . 68
Functional Description . . . . . . . . . . . . . . 68
Block Diagram. . . . . . . . . . . . . . . . . . . . . 70
Operating Modes . . . . . . . . . . . . . . . . . . 71
Register Descriptions . . . . . . . . . . . . . . . 71
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Part 11Packaging . . . . . . . . . . . . . . . . . . . . .168
11.1
56F8037/56F8027 Package and
Pin-Out Information . . . . . . . . . . . 168
Part 6 System Integration Module (SIM) . . . 93
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Introduction . . . . . . . . . . . . . . . . . . . . . . . 93
Features . . . . . . . . . . . . . . . . . . . . . . . . . 94
Register Descriptions . . . . . . . . . . . . . . . 95
Clock Generation Overview . . . . . . . . . 124
Power-Saving Modes . . . . . . . . . . . . . . 124
Resets. . . . . . . . . . . . . . . . . . . . . . . . . . 126
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Interrupts. . . . . . . . . . . . . . . . . . . . . . . . 129
Part 12Design Considerations . . . . . . . . . .171
12.1
12.2
Thermal Design Considerations . . . . . . 171
Electrical Design Considerations . . . . . 172
Part 13Ordering Information . . . . . . . . . . . .173
Part 14Appendix. . . . . . . . . . . . . . . . . . . . . .174
Part 7 Security Features. . . . . . . . . . . . . . . 129
7.1
7.2
Operation with Security Enabled. . . . . . 129
Flash Access Lock and Unlock Mechanisms130
56F8037/56F8027 Data Sheet, Rev. 6
Freescale Semiconductor
5
DSP 与 ARM 处理器
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