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SN74ALVC16501
18 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS261A − JANUARY 1993 − REVISED JULY 1995
D
EPIC
(Enhanced-Performance Implanted
D
D
CMOS) Submicron Process
Member of the Texas Instruments
Widebus
Family
UBT
(Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages
DGG OR DL PACKAGE
(TOP VIEW)
D
D
D
D
description
The SN74ALVC16501 18-bit universal bus
transceiver is designed for low-voltage (3.3-V)
V
CC
operation; it is tested at 2.5-V, 2.7-V, and
3.3-V V
CC
.
Data flow in each direction is controlled by
output-enable (OEAB and OEBA), latch-enable
(LEAB and LEBA), and clock (CLKAB and
CLKBA) inputs. For A-to-B data flow, the device
operates in the transparent mode when LEAB is
high. When LEAB is low, the A data is latched if
CLKAB is held at a high or low logic level. If LEAB
is low, the A-bus data is stored in the latch/flip-flop
on the low-to-high transition of CLKAB. When
OEAB is high, the outputs are active. When OEAB
is low, the outputs are in the high-impedance
state.
OEAB
LEAB
A1
GND
A2
A3
V
CC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
V
CC
A16
A17
GND
A18
OEBA
LEBA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
GND
CLKAB
B1
GND
B2
B3
V
CC
B4
B5
B6
GND
B7
B8
B9
B10
B11
B12
GND
B13
B14
B15
V
CC
B16
B17
GND
B18
CLKBA
GND
Data flow for B to A is similar to that of A to B but uses OEBA, LEBA, and CLKBA. The output enables are
complementary (OEAB is active high and OEBA is active low).
The SN74ALVC16501 is available in TI’s shrink small-outline (DL) and thin shrink small-outline (DGG)
packages, which provide twice the I/O pin count and functionality of standard small-outline packages in the
same printed-circuit-board area.
The SN74ALVC16501 is characterized for operation from − 40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC, UBT, and Widebus are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
1995, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
1
SCAS261A − JANUARY 1993 − REVISED JULY 1995
SN74ALVC16501
18 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
FUNCTION TABLE†
INPUTS
OEAB
L
H
H
H
H
H
H
LEAB
X
H
H
L
L
L
L
CLKAB
X
X
X
↑
↑
H
L
A
X
L
H
L
H
X
X
OUTPUT
B
Z
L
H
L
H
B0‡
B0§
† A-to-B data flow is shown: B-to-A flow is similar but
uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established, provided that CLKAB is
high before LEAB goes low
§ Output level before the indicated steady-state input
conditions were established
logic symbol
†
OEAB
CLKAB
LEAB
1
55
2
27
OEBA
CLKBA
LEBA
30
28
EN1
2C3
C3
G2
EN4
5C6
C6
G5
3D
4
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
5
6
8
9
10
12
13
14
15
16
17
19
20
21
23
24
26
1
1
1
6D
52
51
49
48
47
45
44
43
42
41
40
38
37
36
34
33
31
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
54
B1
A1
3
† This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
SN74ALVC16501
18 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
SCAS261A − JANUARY 1993 − REVISED JULY 1995
logic diagram (positive logic)
OEAB
1
CLKAB
55
LEAB
2
LEBA
28
CLKBA
30
OEBA
27
A1
3
1D
C1
CLK
1D
C1
CLK
54
B1
To 17 Other Channels
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, V
I
(except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.6 V
Input voltage range, V
I
(I/O ports) (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
50 mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±
100 mA
Maximum power dissipation at T
A
= 55°C (in still air) (see Note 3): DGG package . . . . . . . . . . . . . . . . . . 1 W
DL package . . . . . . . . . . . . . . . . . . 1.4 W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the 1994
ABT Advanced BiCMOS Technology
Data Book,
literature number SCBD002B.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
3
SCAS261A − JANUARY 1993 − REVISED JULY 1995
SN74ALVC16501
18 BIT UNIVERSAL BUS TRANSCEIVER
WITH 3 STATE OUTPUTS
recommended operating conditions (see Note 4)
MIN
VCC
VIH
VIL
VI
VO
IOH
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
VCC = 2.3 V
IOL
∆t
/∆v
Low-level output current
Input transition rise or fall rate
VCC = 2.7 V
VCC = 3 V
0
−40
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0
0
2.3
1.7
2
0.7
0.8
VCC
VCC
−12
−12
−24
12
12
24
10
85
ns / V
°C
mA
mA
V
V
V
V
MAX
3.6
UNIT
V
High-level output current
TA
Operating free-air temperature
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251−1443
•
•
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