HYS64/72D32000/64020GU
Unbuffered DDR-I SDRAM-Modules
2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
256 MByte & 512 MByte Modules
PC1600 & PC2100
• 184-pin Unbuffered 8-Byte Dual-In-Line
DDR-I SDRAM non-parity and ECC-Modules
for PC and Server main memory applications
• One bank 32M
×
64, 32M x 72 and two bank
64M x 64, 64M
×
72 organization
• JEDEC standard Double Data Rate
Synchronous DRAMs (DDR-I SDRAM)
Single + 2.5 V (
±
0.2 V) power supply
• Built with 256 Mbit DDR-I SDRAMs organised
as 32Mb x 8 in 66-Lead TSOPII package
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• Performance:
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E
2
PROM
• Jedec standard MO-206 form factor:
133.35 mm
×
31.75 mm
×
4.00 mm max.
• Jedec standard reference layout
• Gold plated contacts
-7
Component Speed Grade
Module Speed Grade
f
CK
f
CK
-8
PC1600
125
100
Unit
DDR266A DDR200
PC2100
143
133
MHz
MHz
Clock Frequency (max.) @ CL = 2.5
Clock Frequency (max.) @ CL = 2
The HYS64/72D32000GU and HYS64/72D64020GU are industry standard 184-pin 8-byte Dual in-
line Memory Modules (DIMMs) organized as 32M
×
64 and 64M
×
64 for non-parity and 32M x 72
and 64M x 72 for ECC main memory applications. The memory array is designed with 256Mbit
Double Data Rate Synchronous DRAMs. A variety of decoupling capacitors are mounted on the PC
board. The DIMMs feature serial presence detect based on a serial E
2
PROM device using the 2-pin
I
2
C protocol. The first 128 bytes are programmed with configuration data and the second 128 bytes
are available to the customer.
INFINEON Technologies
1
12.01
HYS64/72D32000/64020GU
Unbuffered DDR-I SDRAM-Modules
Ordering Information
Type
PC2100 (CL=2):
HYS64D32000GU-7-A
HYS64D32000GU-7-B
HYS72D32000GU-7-A
HYS72D32000GU-7-B
HYS64D64020GU-7-A
HYS64D64020GU-7-B
HYS72D64020GU-7-A
HYS72D64020GU-7-B
PC1600 (CL=2):
HYS64D32000GU-8-A
HYS64D32000GU-8-B
HYS72D32000GU-8-A
HYS72D32000GU-8-B
HYS64D64020GU-8-A
HYS64D64020GU-8-B
HYS72D64020GU-8-A
HYS72D64020GU-8-B
Note:
PC1600-20220-B1
PC1600-20220-A1
PC1600-20220-B1
PC1600-20220-A1
PC1600-20220-B1
PC1600-20220-B1
one bank 256 MB DIMM
one bank 256 MB DIMM
one bank 256 MB ECC-DIMM
one bank 256 MB ECC-DIMM
two banks 512 MB DIMM
two banks 512 MB ECC-DIMM
256 MBit
256 MBit
256 Mbit
256 Mbit
256 MBit
256 MBit
PC2100-20330-B1
PC2100-20330-A1
PC2100-20330-B1
PC2100-20330-A1
PC2100-20330-B1
PC2100-20330-B1
one bank 256 MB DIMM
one bank 256 MB DIMM
one bank 256 MB ECC-DIMM
one bank 256 MB ECC-DIMM
two banks 512 MB DIMM
two banks 512 MB ECC-DIMM
256 MBit
256 MBit
256 Mbit
256 Mbit
256 MBit
256 MBit
Compliance Code
Description
SDRAM
Technology
All part numbers end with a place code, designating the silicon-die revision. Reference information
available on request. Example: HYS 72D32000GU-8-A, indicating Rev.A dies are used for the SDRAM
components.
The Compliance Code is printed on the module labels and describes the speed sort fe. “PC2100”, the
latencies (f.e. “20330” means CAS latency = 2, trcd latency = 3 and trp latency =3 ) and the Raw Card
used for this module.
INFINEON Technologies
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12.01
HYS64/72D32000/64020GU
Unbuffered DDR-I SDRAM-Modules
Pin Definitions and Functions
A0 - A12
BA0, BA1
DQ0 - DQ63
CB0 - CB7
RAS
CAS
WE
CKE0 - CKE1
DQS0 - DQS8
CLK0 - CLK2,
CLK0 - CLK2
DM0 - DM8
DQS9 - DQS17
Address Inputs
Bank Selects
Data Input/Output
Check Bits (x72 organization only)
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
SDRAM low data strobes
SDRAM clock (positive lines)
SDRAM clock (negative lines)
SDRAM low data mask/
high data strobes
S0, S1
V
DD
V
SS
V
DDQ
V
DDID
V
REF
V
DDSPD
SCL
SDA
SA0 - SA2
NC
Chip Selects
Power (+ 2.5 V)
Ground
I/O Driver power supply
VDD Indentification flag
I/O reference supply
Serial EEPROM power supply
Serial bus clock
Serial bus data line
slave address select
no connect
note: S1 and CKE1 are used on two bank modules only
Address Format
Density
256 MB
256 MB
512 MB
512 MB
Organization
32M x 64
32M x 72
64M
×
64
64M
×
72
Memory
Banks
1
1
2
2
SDRAMs
32M x 8
32M x 8
32M x 8
32M x 8
# of
SDRAMs
8
9
16
18
# of row/bank/
columns bits
13/2/10
13/2/10
13/2/10
13/2/10
Refresh
8k
8k
8k
8k
Period
64 ms
64 ms
64 ms
64 ms
Interval
7.8
µ
s
7.8
µ
s
7.8
µ
s
7.8
µ
s
INFINEON Technologies
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12.01
HYS64/72D32000/64020GU
Unbuffered DDR-I SDRAM-Modules
Pin Configuration
PIN#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Frontside
Symbol
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CLK1
CLK1
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
NC / CB0
NC / CB1
VDD
NC / DQS8
PIN#
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
Frontside
Symbol
A0
NC / CB2
VSS
NC / CB3
BA1
KEY
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDDQ
WE
DQ41
CAS
VSS
DQS5
DQ42
DQ43
VDD
NC
DQ48
DQ49
VSS
CLK2
CLK2
VDDQ
DQS6
DQ50
DQ51
VSS
VDDID
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
PIN#
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
Backside
Symbol
VSS
DQ4
DQ5
VDDQ
DM0/DQS9
DQ6
DQ7
VSS
NC
NC
NC
VDDQ
DQ12
DQ13
DM1/DQS10
VDD
DQ14
DQ15
CKE1
VDDQ
NC (BA2)
DQ20
NC / A12
VSS
DQ21
A11
DM2/DQS11
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3/DQS12
A3
DQ30
VSS
DQ31
NC / CB4
NC / CB5
VDDQ
CK0
CK0
VSS
PIN#
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
Backside
Symbol
NC / DM8/DQS17
A10
NC / CB6
VDDQ
NC / CB7
KEY
VSS
DQ36
DQ37
VDD
DM4/DQS13
DQ38
DQ39
VSS
DQ44
RAS
DQ45
VDDQ
S0
S1
DM5/DQS14
VSS
DQ46
DQ47
NC
VDDQ
DQ52
DQ53
NC (A13)
VDD
DM6/DQS15
DQ54
DQ55
VDDQ
NC
DQ60
DQ61
VSS
DM7/DQS16
DQ62
DQ63
VDDQ
SA0
SA1
SA2
VDDSPD
Note: Pins 44, 45, 47, 49, 51, 134, 135, 140 and 144 are NC (“no-connects”) on x64 organised non-ECC
modules. A12 is used for 256Mbit based modules only
INFINEON Technologies
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12.01
HYS64/72D32000/64020GU
Unbuffered DDR-I SDRAM-Modules
DQS0
DM0/DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
S0
DQS4
DM4/DQS13
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D0
DQS
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D4
DQS
DQS1
DM1/DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D1
DQS
DQS5
DM5/DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D5
DQS
DQS2
DM2/DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D2
DQS
DQS6
DM6/DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D6
DQS
DQS3
DM3/DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D3
DQS
DQS7
DM7/DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM
I/O 7
I/O 6
I/O 1
I/O 0
I/O 5
I/O 4
I/O 3
I/O 2
CS
D7
DQS
* Clock Wiring
Serial PD
SDA
SCL
A0
SA0
BA0 - BA1
A0 -A11, A12
V
DD,
V
DDQ
VREF
V
SS
V
DDID
BA0, BA1: SDRAMs D0 - D7
A0 - A11,A12: SDRAMs D0 - D7
RAS
D0 - D7
D0 - D7
D0 - D7
CAS
CKE0
WE
RAS: SDRAMs D0 - D7
CAS: SDRAMs D0 - D7
CKE: SDRAMs D0 - D7
W E : SDRAMs D0 - D7
A1
SA1
A2
SA2
Clock
Input
*CK0/CK0
*CK1/CK1
*CK2/CK2
SDRAMs
2 SDRAMs
3 SDRAMs
3 SDRAMs
* Wire per Clock Loading
Table/W iring Diagrams
Notes:
1. DQ-to-I/O wiring is shown as recom-
mended but may be changed.
2. DQ/DQS/DM/CKE/S relationships must
be maintained as shown.
3. DQ, DQS, DM/DQS resistors: 22 Ohms.
4. VDDID strap connections
(for memory device VDD, VDDQ):
STRAP OUT (OPEN): VDD = VDDQ
Block Diagram: One Bank 32M x 64 DDR-I SDRAM DIMM Module
HYS64D32000GU using x8 organized SDRAMs
INFINEON Technologies
5
12.01
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