HB56UW865DB-6AU
64MB Unbuffered EDO DRAM S.O.DIMM
8-Mword
×
64-bit, 1 Bank Module
(8 pcs of 8M
×
8 components)
ADE-203-842A (Z)
Rev. 1.0
Oct. 15, 1997
Description
The HB56UW865DB-AU Series is a 8 M
×
64 Dynamic RAM Small Outline Dual In-line Memory
Module (S. O. DIMM), mounted 8 pieces of 64-Mbit DRAM (HM5165805AU) sealed in TSOP package
and 1 piece of serial EEPROM (24C02) for Presence Detect (PD). The HB56UW865DB-AU Series offers
Extended Data Out (EDO) Page Mode as a high speed access mode. An outline of the HB56UW865DB-
AU Series is 144-pin Zig Zag Dual tabs socket type compact and thin package. Therefore, the
HB56UW865DB-AU Series makes high density mounting possible without surface mount technology. The
HB56UW865DB-AU Series provides common data inputs and outputs. Decoupling capacitors are
mounted beside each TSOP on the its module board.
Features
•
144-pin Zig Zag Dual tabs socket type
Outline: 67.60 mm (Length)
×
25.40 mm (Height)
×
3.80 mm (Thickness)
Lead pitch : 0.80 mm
•
Single 3.3 V (±0.3 V)
•
High speed
Access time: t
RAC
= 60 ns (max)
Access time: t
CAC
= 15 ns (max)
•
Low power dissipation
Active mode: 4.76 W (max)
Standby mode (TTL): 57.6 mW (max)
Standby mode (CMOS): 8.6 mW (max)
•
JEDEC standard outline S. O. DIMM
•
EDO page mode capability
•
4096 refresh cycles: 128 ms
HB56UW865DB-6AU
Serial PD Matrix*
1
Byte No. Function described
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Number of bytes used by
module manufacturer
Total SPD memory size
Memory type
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
×
1
1
0
0
1
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
×
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
×
0
0
1
1
1
1
0
1
0
1
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
0
×
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
0
×
0
0
1
1
1
1
0
0
1
0
1
0
0
0
0
0
1
0
1
0
0
0
0
0
1
1
0
×
0
1
0
1
0
1
0
0
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
1
0
1
0
×
0
0
1
0
1
1
80
08
02
0C
0B
01
40
00
01
3C
0F
00
83
08
00
00
00
01
BA
07
00
××
48
42
35
36
55
57
*
2
(ASCII-
8bit code)
H
B
5
6
U
W
Hitachi
Rev. 1
128
256 byte
EDO
12
11
1
64 bits
0 (+)
LVTTL
t
RAC
= 60 ns
t
CAC
= 15 ns
Non parity
Self refresh
(31.3
µs)
8M
×
8
Number of row addresses bits 0
Number of column addresses 0
bits
Number of banks
Module data width
0
0
Module data width (continued) 0
Module interface signal levels 0
RAS
access time
CAS
access time
Module configuration type
Refresh rate/type
DRAM width
Error checking DRAM data
width
0
0
0
1
0
0
0
0
0
1
0
0
×
0
0
0
0
0
0
15 to 31 Reserved for future offerings
32 to 61 Superset information
62
63
64
SPD revision
Checksum for bytes 0 to 62
Manufacturer’s JEDEC ID
code
65 to 71 Manufacturer’s JEDEC ID
code
72
73
74
75
76
77
78
Manufacturing location
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
Manufacturer’s part number
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
