www.fairchildsemi.com
KH232
Low Distortion Wideband Op Amp
Features
s
s
s
s
s
s
s
General Description
The KH232 is a wideband low distortion operational
amplifier designed specifically for high speed, low gain
applications requiring wide dynamic range. Utilizing a
current feedback architecture, the KH232 offers high
speed performance while maintaining DC precision.
The KH232 offers precise gains from ±1 to ±5 with a
true 0.1% linearity and provides stable, oscillation-
free operation across the entire gain range without
external compensation. The KH232, a pin compatible
enhanced version of the KH231, reduces 2nd and 3rd
harmonic distortion to an extremely low -69dBc at
20MHz (2V
pp
, R
L
= 100Ω). Additional features provided
by the KH232 include a small signal bandwidth of
270MHz, a large signal bandwidth of 95MHz and a
3000V/µs slew rate. The input offset voltage is typically
1mV with an input offset drift of 10µV/°C.
The KH232 combines these high performance features
with its 0.05% settling time of 15ns and its 100mA
drive capability to provide high speed, high resolution
A/D and D/A converter systems with an attractive
solution for driving and buffering. Wide dynamic
range systems such as radar and communication
receivers requiring low harmonic distortion and low
noise will find the KH232 to be an excellent choice. As
a line driver, the KH232 set at a gain of 2 cancels
matched line losses.
The KH232 is constructed using thin film resistor/bipolar
transistor technology, and is available in the following
versions:
Supply
Voltage
-69dBc 2nd and 3rd harmonics at 20MHz
-3dB bandwidth of 270MHz
0.05% settling in 15ns
3000V/µs slew rate
1mV input offset voltage, 10µV/°C drift
±10V, 100mA max output
Direct replacement for CLC232
Applications
s
s
s
s
s
s
s
Flash A/D drivers
DAC current-to-voltage conversion
Wide dynamic range IF amps
VCO drivers
DDS postamps
Radar/communication receivers
Precision line drivers
Bottom View
I
CC
Adjust
Case
ground
GND
7
Adjust -V
CC
8
9
-V
CC
V+ 6
10
Collector
Supply
Output
KH232AI
KH232AK
KH232AM
-25°C to +85°C
-55°C to +125°C
-55°C to +125°C
Non-Inverting
Input
Inverting
Input
Not
Connected
+
V- 5
NC 4
3
Case
ground
GND
2
4
4
-
11 V
o
12
+V
CC
Collector
Supply
1
Supply
Voltage
KH232HXC
KH232HXA
-55°C to +125°C
-55°C to +125°C
12-pin TO-8 can
12-pin TO-8 can, features
burn-in & hermetic testing
12-pin TO-8 can,
environmentally
screened and electrically
tested to MIL-STD-883
SMD#: 5962-9166501HXC
SMD#: 5962-9166501HXA
Adjust +V
CC
I
CC
Adjust
Typical Performance
Gain Setting
Parameter
1
2
5
-1
-2
-5
Units
MHz
ns
V/ns
ns
-3dB bandwidth
430 270 135 220 175 110
rise time (2V)
1.8 2.0 2.5 2.0 2.2 2.9
slew rate
2.5 3.0 3.0 3.0 3.0 3.0
settling time (to 0.1%) 12 12 12 12 12 15
Pins 2 and 8 are used to adjust the sup-
ply current or to adjust the offset voltage
(see text). These pins are normally left
unconnected.
REV. 1A February 2001
DATA SHEET
KH232
KH232 Electrical Characteristics
PARAMETERS
Ambient Temperature
Ambient Temperature
FREQUENCY DOMAIN RESPONSE
✝
-3dB bandwidth (note 2)
large-signal bandwidth
gain flatness (note 2)
peaking
peaking
rolloff
group delay
linear phase deviation
reverse isolation
non-inverting
inverting
KH232AI
(T
A
= +25°C, A
v
= +2V, V
CC
= ±15V, R
L
= 100Ω, R
f
= 250Ω; unless specified)
TYP
+25°C
+25°C
270
165
95
0.1
0.1
0.4
3.5 ± 0.5
0.5
53
36
MIN & MAX RATINGS
-25°C
-55°C
>200
>145
>80
<0.6
<1.5
<0.6
–
<2.0
>43
>26
<2.4
<7.0
–
<22
<15
>2.5
–
<-64
<-64
<3.2
<23
<2.6
<-154
<64
<64
<4.0
<25
<29
<125
<31
<200
>45
>40
<27
>100
<2.5
–
>±11
+25°C
+25°C
>200
>145
>80
<0.3
<0.3
<0.6
–
<2.0
>43
>26
<2.3
<6.5
–
<17
<10
>2.5
–
<-64
<-64
<3.2
<23
<2.6
<-154
<64
<64
<2.0
<25
<21
<125
<15
<200
>45
>40
<27
>200
<2.5
–
>±11
+85°C
+125°C
>200
>120
>60
<0.6
<0.8
<1.0
–
<2.0
>43
>26
<2.7
<6.5
–
<22
<15
>1.8
–
<-56
<-64
<3.5
<25
<2.9
<-153
<72
<72
<4.5
<25
<31
<125
< 35
<200
>45
>40
<29
>400
<2.5
–
>±11
MHz
MHz
MHz
dB
dB
dB
ns
°
dB
dB
ns
ns
ns
ns
%
V/ns
ns
dBc
dBc
SSBW
SSBW
FPBW
GFPL
GFPH
GFR
GD
LPD
RINI
RIIN
TRS
TRL
TS
TSP
OS
SR
OR
HD2
HD3
UNITS
SYM
CONDITIONS
KH232AK/AM/HXC/HXA
V
o
≤0.63V
pp
V
o
≤2V
pp
V
o
≤10V
pp
V
o
≤0.63V
pp
0.1 to 50MHz
>50MHz
at 100MHz
to 100MHz
to 100MHz
✝
✝
✝
TIME DOMAIN RESPONSE
rise and fall time
settling time to 0.05%
to 0.1%
overshoot
slew rate (overdriven input)
overload recovery
<50ns pulse, 200% overdrive
NOISE AND DISTORTION RESPONSE
✝
2nd harmonic distortion
✝
3rd harmonic distortion
equivalent input noise
voltage
inverting current
non-inverting current
noise floor
integrated noise
integrated noise
STATIC, DC PERFORMANCE
* input offset voltage
average temperature coefficient
* input bias current
average temperature coefficient
* input bias current
average temperature coefficient
* power supply rejection ratio
common mode rejection ratio
* supply current
MISCELLANEOUS PERFORMANCE
non-inverting input resistance
non-inverting input capacitance
output impedance
output voltage range
2V step
10V step
5V step
2.5V step
5V step
<1% error
2.0
5.0
15
12
5
3.0
120
2V
pp
, 20MHz
2V
pp
, 20MHz
>100kHz
>100kHz
>100kHz
>100kHz
1kHz to 200MHz
5MHz to 200MHz
-69
-69
2.8
20
2.3
-155
57
57
1
10
5.0
50
10
125
50
46
25
400
1.3
5, 37
±12
VN
nV/√Hz
ICN
pA/√Hz
pA/√Hz NCN
dBm(1Hz) SNF
µVrms
INV
µVrms
INV
mV
µV/°C
µA
nA/°C
µA
nA/°C
dB
dB
mA
kΩ
pF
Ω,
nH
V
VIO
DVIO
IBN
DIBN
IBI
DIBI
PSRR
CMRR
ICC
RIN
CIN
RO
VO
non-inverting
inverting
no load
DC
@ 100MHz
no load
Min/max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Outgoing quality levels are
determined from tested parameters.
Absolute Maximum Ratings
V
CC
I
o
common mode input voltage, V
o
differential input voltage
thermal resistance
junction temperature
operating temperature
storage temperature
lead temperature (soldering 10s)
±20V
±100mA
|V
CC
| >15V ±(30-|V
CC
|)V
|V
CC
|
≤
15V ±|V
CC
|V
±3V
(see thermal model)
+175°C
AI: -25°C to +85°C
AK/AM/HXC/HXA: -55°C to +125°C
-65°C to +150°C
+300°C
Recommended Operating Conditions
V
CC
I
o
common mode input voltage
gain range
note 1:
*
✝
±5V to ±15V
±75mA
±(|V
CC
| -5)V
±1 to ±5
note 2:
AI/AK/AM/HXC/HXA 100% tested at +25°C
AK/AM/HXC/HXA
100% tested at +25°C and sample
tested at -55°C and +125°C
✝
AI
sample tested at +25°C
The output amplitude used in testing is 0.63V
pp
. Performance
is guaranteed for conditions listed.
2
REV. 1A February 2001
KH232
DATA SHEET
KH232 Typical Performance Characteristics
(T
Non-Inverting Frequency Response
Normalized Magnitude (1dB/div)
Normalized Magnitude (1dB/div)
Gain
A
v
= 1
Gain
A
= +25°C, A
v
= +2, V
CC
= ±15V, R
L
= 100Ω, R
f
= 250Ω; unless specified)
Settling Time vs. C
L
35
R
s
Inverting Frequency Response
70
C
L
A
v
= +2
A
v
= -2
30
Phase
A
v
= 5
Phase
Settling Time (ns)
A
v
= 2
1k
60
50
Phase (45 deg/div)
Phase (45 deg/div)
25
R
S
R
S
A
v
= -5
A
v
= -5
A
v
= -2
A
v
= -1
A
v
= -1
20
T
S
40
30
20
10
0
100
1000
(Ω)
A
v
= 5
A
v
= 2
A
v
= 1
15
10
5
0
150
300
0
150
300
Frequency (MHz)
Bandwidth vs. V
CC
1.2
Frequency (MHz)
Frequency Response vs. R
L
R
L
= 500
Gain
C
L
(pF)
Large Signal Non-Inverting Gain & Phase
A
v
= 2
V
o
= 10V
pp
Relative Bandwidth
1.0
R
L
= 200
Pins 1 and 2 Shorted
Pins 8 and 9 shorted
Phase (45 deg/div)
(1dB/div)
0.8
R
L
= 50
R
L
= 100
(1dB/div)
0
Phase
0.6
A
v
= 2
0.4
4
6
8
10
12
14
16
0
150
300
150
300
±V
CC
(V)
2nd Harmonic Distortion
-20
-30
-20
-30
Frequency (MHz)
3rd Harmonic Distortion
-40
-45
-50
V
o
= 2V
pp
Frequency (MHz)
2nd and 3rd Harmonic Distortion
Distortion (dBc)
Distortion (dBc)
-40
8V
pp
-40
8V
pp
Distortion (dBc)
-55
-60
-65
-70
-75
-80
-85
-90
2nd
-50
4V
pp
-50
4V
pp
-60
-70
2V
pp
-60
-70
2V
pp
3rd
-80
1V
pp
-80
1V
pp
-90
1
10
100
-90
1
10
100
1
10
100
Frequency (Hz)
2-Tone, 3rd Order Intermod. Intercept
50
100
50Ω
P
out
Frequency (Hz)
Equivalent Input Noise
100
PSRR
Frequency (MHz)
CMRR and PSRR
Noise Voltage (nV/√Hz)
45
Interdept Point (dBm)
PSRR/CMRR (dB)
50Ω
50
CMRR
Noise Current (pA/√Hz)
40
35
30
25
20
15
0
10
20
30
40
50
60
70
80
90 100
Inverting Current 20pA/√Hz
40
30
20
10
10
10
Voltage 2.8nV/√Hz
Non-Inverting Current 2.3pA/√Hz
1
100
1k
10k
100k
1M
10M
1
100M
1
10
100
1k
10k
100k
1M
10M 100M
Frequency (MHz)
Small Signal Pulse Response
Output Voltage (400mV/div)
Frequency (Hz)
Large Signal Pulse Response
0.20
0.15
Frequency (Hz)
Settling Time
Output Voltage (2V/div)
Settling Error (%)
A
v
= 2
A
v
= 2
0.10
0.05
0
-0.05
-0.10
-0.15
-0.20
5ns/div
50ns/div
A
v
= -2
A
v
= -2
Time (5ns/div)
Time (5ns/div)
Time (ns)
REV. 1A February 2001
3
DATA SHEET
KH232
Operation
The KH232 is based on the current feedback op amp
topology, a design that uses current feedback instead of
the usual voltage feedback.
The use of the KH232 is basically the same as that of the
conventional op amp (see Figures 1 and 2). Since the
device is designed specifically for low gain applications,
the best performance is obtained when the circuit is used
at gains between ±1 and ±5. Additionally, performance is
optimum when a 250Ω feedback resistor is used.
Layout Considerations
To assure optimum performance the user should follow
good layout practices which minimize the unwanted
coupling of signals between nodes. During initial bread-
boarding of the circuit use direct point to point wiring,
keeping the lead lengths to less than 0.25”. The use of
solid, unbroken ground plane is helpful. Avoid wire-wrap
type pc boards and methods. Sockets with small, short
pin receptacles may be used with minimal performance
degradation although their use is not recommended.
During pc board layout keep all traces short and direct
The resistive body of R
g
should be as close as possible
to pin 5 to minimize capacitance at that point. For the
same reason, remove ground plane from the vicinity of
pins 5 and 6. In other areas, use as much ground plane
as possible on one side of the board. It is especially
important to provide a ground return path for current from
the load resistor to the power supply bypass capacitors.
Ceramic capacitors of 0.01 to 0.1µf (with short leads)
should be less than 0.15 inches from pins 1 and 9.
Larger tantalum capacitors should be placed within one
inch of these pins. V
CC
connections to pins 10 and 12
can be made directly from pins 9 and 1, but better supply
rejection and settling time are obtained if they are
separately bypassed as in figures 1 and 2. To prevent
signal distortion caused by reflections from impedance
mismatches, use terminated microstrip or coaxial cable
when the signal must traverse more than a few inches.
Since the pc board forms such an important part of the
circuit, much time can be saved if prototype boards of any
high frequency sections are built and tested early in the
design phase. Evaluation boards designed for either
inverting or non-inverting gains are available.
Offset Voltage Adjustment
If trimming of the input offset voltage (V
os
= V
ni
-V
in
) is
desired, a resistor value of 10kΩ to 1MΩ placed between
pins 8 and 9 will cause V
os
to become more negative by
8mV to 0.2mV respectively. Similarly, a resistor placed
between pins 1 and 2 will cause V
os
, to become more
positive.
Thermal Considerations
At high ambient temperatures or large internal power
dissipations, heat sinking is required to maintain
acceptable junction temperatures. Use the thermal
model on the previous page to determine junction
temperatures. Many styles of heat sinks are available for
TO-8 packages; the Thermalloy 2240 and 2268 are good
examples. Some heat sinks are the radial fin type which
cover the pc board and may interfere with external
components. An excellent solution to this problem is to
use surface mounted resistors and capacitors. They
have a very low profile and actually improve high
frequency performance. For use of these heat sinks with
conventional components, a 0.1” high spacer can be inserted
under the TO-8 package to allow sufficient clearance.
REV. 1A February 2001
+15V
3.9
33Ω
0.1
6
1
12
11
10
3,7
9
.01
Capactance in
µF
V
in
R
i
49.9Ω
R
g
+
-
KH232
5
V
o
250Ω
R
L
100Ω
-15V
3.9
33Ω
0.1
.01
A
v
=
1+
R
f
R
g
R
f
= 250Ω
Figure 1: Recommended non-inverting gain circuit
+15V
3.9
33Ω
0.1
100Ω
R
g
6
1
12
11
10
3,7
9
.01
Capactance in
µF
+
-
KH232
5
V
o
250Ω
R
L
100Ω
V
in
R
i
-15V
3.9
33Ω
0.1
.01
R
f
A
v
= −
R
g
R
f
= 250Ω
For Z
in
= 50Ω, select
R
g
|| R
i
= 50Ω
Figure 2: Recommended inverting gain circuit
4
KH232
DATA SHEET
T
case
100°C/W
T
j(pnp)
P
pnp
100°C/W
T
j(npn)
P
npn
48
°
C/W
T
j(circuit)
P
circuit
+
-
T
ambient
θ
ca
Other methods of heat sinking may be used, but for
best results, make contact with the base of the KH232
package, use a large thermal capacity heat sink and use
forced air convection.
Low V
CC
Operation: Supply Current Adjustment
The KH232 is designed to operate on supplies as low
as ±5V. In order to improve full bandwidth at reduced
supply voltages, the supply current (I
CC
) must be
increased. The plot of Bandwidth vs. V
CC
, shows the
effect of shorting pins 1 and 2 and pins 8 and 9; this
will increase both bandwidth and supply current. Care
should be taken to not exceed the maximum junction
temperatures; for this reason this technique should not be
used with supplies exceeding ±10V. For intermediate val-
ues of V
CC
, external resistors between pins 1 and 2 and
pins 8 and 9 can be used.
P
(circuit)
= (I
CC
)((+V
CC
) – (V
CC
)) where I
CC
= 14mA at ±15V
P
(xxx)
= [(±V
CC
) – V
out
– (I
col
) (R
col
+ 4)] (I
col
) (%Duty)
For positive V
o
and V
CC
, this is the power in the npn
device. For negative V
o
and V
CC
, this is the power in the
pnp device.
I
col
= V
o
/R
L
or 12mA, whichever is greater. (Include feed-
back R in R
L
.)
R
col
is a resistor (33Ω recommended) between the xxx
collector and ±V
CC
.
The limiting factor for output current and voltage is junction
temperature. Of secondary importance is I
(out)
, which
should not exceed 150mA.
T
j(pnp)
= P
(pnp)
(100 +
θ
ca
) + (P
(cir)
+ P
(npn)
)(θ
ca
) + T
a
,
similar for T
j(npn)
.
T
j(cir)
= P
(cir)
(48 +
θ
ca
) + (P
(pnp)
+ P
(npn)
)(θ
ca
) + T
a
.
θ
ca
= 65°C/W for the KH232 without heat sink in still air.
35°C/W for the KH232 with a Thermalloy 2268A
heat sink in still air.
15°C/W for the KH232 with a Thermalloy 2268A
heat sink at 300 ft/min air.
(Thermalloy 2240A works equally as well.)
For example, with the KH232 operating at ±15V while
driving a 100Ω load at 15V
pp
output (50% duty cycle
pulse waveform, DC = 0), P
(npn)
= P
(pnp)
= 190mW (R
col
= 33) and P
(cir)
= 0.42W. Then with the Thermalloy
2268 heat sink and air flow of 300 ft/min the output
transistors’ T
j
is 31°C above ambient and worst case T
j
in
the rest of the circuit is 32°C above ambient. In still air,
however, the rise in T
j
is 47°C and 48°C, respectively.
With no heat sink, the rise in T
j
is 71°C and 72°C,
respectively! Under most conditions,
HEAT SINKING IS
REQUIRED.
REV. 1A February 2001
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
