hmp
Description
1M x 32 SRAM MODULE
PUMA 84S32000 - 012/015/020
Issue 2.0 : March 2002
Features
•
•
Very fast access times of 12/15/20 ns .
JEDEC 84 'J' leaded plastic Surface Mount
Package.
•
•
•
Single 5V±10% Power supply.
User Configurable as 8 / 16 / 32 bit wide output.
Operating Power
Low Power Standby
•
•
Fully Static operation.
Multiple ground pins for maximum noise immunity.
(32-BIT)
CMOS
5.28 W (max)
550 mW (max)
Elm Road, West Chirton Industrial Estate, North Shields,
NE29 8SE, ENGLAND. TEL +44 (0191) 2930500. FAX +44
(0191) 2590997
The PUMA 84S32000 is a 32Mbit CMOS High Speed
Static RAM organised as 1M x 32 in a JEDEC 84 pin
surface mount J-leaded PLCC, available with access
times of 12, 15, and 20ns. The output width is user
configurable as 8, 16 or 32 bits using eight Chip Selects
(CS1~8).
The device features low power standby, multiple ground
pins for maximum noise immunity and TTL compatible
inputs and outputs. The PUMA 84S32000 offers a
dramatic space saving advantage over eight standard
512Kx8 devices.
Block Diagram
A0 - A18
WE
OE
512K x 8
SRAM
CS1
512K x 8
SRAM
CS2
512K x 8
SRAM
CS3
D0 - D7
CS5
512K x 8
SRAM
512K x 8
SRAM
D0 - D7
Pin Definition
NC
NC
D16
A18
A17
CS4
CS3
CS2
CS1
NC
VCC
CS8
CS7
CS6
CS5
OE
WE
A16
A15
A14
D15
11 10 9
8
7
6
5
4
3
2
1 84 83 82 81 80 79 78 77 76 75
74
73
72
71
70
69
68
D8 - D15
CS6
D8 - D15
D16 - D23
CS7
512K x 8
SRAM
D16 - D23
512K x 8
SRAM
CS4
D24 - D31
CS8
512K x 8
SRAM
D24 - D31
NC
NC
D17
D18
D19
GND
D20
D21
D22
D23
VCC
D24
D25
D26
D27
GND
D28
D29
D30
NC
NC
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
PUMA 84S32000
VIEW
FROM
ABOVE
67
66
65
64
63
62
61
60
59
58
57
56
55
54
NC
NC
D14
D13
D12
GND
D11
D10
D9
D8
VCC
D7
D6
D5
D4
GND
D3
D2
D1
NC
NC
NC
NC
D31
A6
A5
A4
A3
A2
A1
A0
VCC
Pin Functions
Address Inputs
Data Input/Output
Chip Select
Write Enable
Output Enable
No Connect
Power (+5V)
Ground
A0 ~ A18
D0 ~ D31
CS1 ~ 8
WE
OE
NC
V
CC
GND
Package Details
Plastic 84 J-Leaded JEDEC PLCC
A13
A12
A11
A10
A9
A8
A7
D0
NC
NC
PUMA 84S32000
- 012/015/020
Issue 2.0 : March 2002
DC OPERATING CONDITIONS
Absolute Maximum Ratings
(1)
Parameter
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Symbol
V
T(2)
P
T
T
STG
Min
-0.5
-
-65
Typ
-
-
-
Max
7.0
5.0
150
Unit
V
W
o
C
Notes : (1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at those or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
(2) V
T
can be -2.0V pulse of less than 8ns.
Recommended Operating Conditions
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
Symbol
V
CC
V
IH
V
IL
T
A
T
AI
Min
4.5
2.2
-0.3
0
-40
Typ
5.0
-
-
-
-
Max
5.5
V
CC
+0.5
0.8
70
85
Unit
V
V
V
o
C
o
C (Suffix I)
(Commercial)
(Industrial)
DC Electrical Characteristics
(V
CC
=5V±10%, -40 to 85 C)
Parameter
I/P Leakage Current
Address,OE,WE
Symbol Test Condition
I
LI
I
LO
32-bit mode
16-bit mode
8-bit mode
Min Typ
-20
-20
-
-
-
-
-
-
2.4
-
-
-
-
-
-
-
-
-
max
20
20
960
640
480
320
100
0.4
-
Unit
µA
µA
mA
mA
mA
mA
mA
V
V
0V < V
IN
< V
CC
CS = V
IH,
V
I/O
= GND to V
CC
Min. Cycle, CS = V
IL
, f=f
MAX
, I
OUT
= 0mA
As Above.
As Above.
CS = V
IH
, f=f
MAX
CS
>
V
CC
-0.2V, 0.2<V
IN
<V
CC
-0.2V, f=0
I
OL
= 8.0mA
I
OH
= -4.0mA
Output Leakage Current
Operating Supply Current
I
CC32
I
CC16
I
CC8
I
SB1
I
SB2
V
OL
V
OH
Standby Supply Current
Output Voltage
TTL levels
CMOS levels
Notes :
1/ Typical values are at V
CC
=5.0V,T
A
=25
o
C and specified loading.
2/ CS above refers to CS1~4 / CS5~8 for 32 bit mode
3/
At f=f
MAX
address and data inputs are cycling at maximum frequency.
2
PUMA 84S32000
- 012/015/020
Issue 2.0 : March 2002
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Note: Capacitance calculated, not measured.
Parameter
Input Capacitance
I/P Capacitance
I/O Capacitance
(Address,OE,WE)
(Other)
Worst case (8-bit)
Symbol Test Condition
C
IN1
C
IN2
C
I/O
V
IN
= 0V
V
IN
= 0V
V
I/O
= 0V
max
70
12
62
Unit
pF
pF
pF
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 3ns
* Input and Output timing reference levels: 1.5V
* Output load: see diagram
* V
CC
=5V±10%
Output Load
I/O Pin
166Ω
1.76V
30pF
Operation Truth Table
CS
H
L
L
L
L
OE
X
L
H
L
H
WE
X
H
L
L
H
DATA PINS
High Impedance
Data Out
Data In
Data In
High-Impedance
SUPPLY CURRENT
I
SB1
, I
SB2
I
CC32
, I
CC16
, I
CC8
I
CC32
, I
CC16
, I
CC8
I
CC32
, I
CC16
, I
CC8
I
SB1
, I
SB2
MODE
Standby
Read
Write
Write
High-Z
Notes : H = V
IH
: L =V
IL
: X = V
IH
or V
IL
The above table reflects the operation of each of the RAM's on the module. Care should be taken to avoid
bus contention on data lines using chip select signals.
3
PUMA 84S32000
- 012/015/020
Issue 2.0 : March 2002
AC OPERATING CONDITIONS
Read Cycle
012
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection to Output in Low Z
Output Enable to Output in Low Z
Chip Deselection to O/P in High Z
Output Disable to Output in High Z
015
min
15
-
-
-
3
3
0
0
0
020
min
20
-
-
-
3
3
0
0
0
Symbol
t
RC
t
AA
t
ACS
t
OE
t
OH
t
CLZ
t
OLZ
t
CHZ
t
OHZ
min
12
-
-
-
3
3
0
0
0
max
-
12
12
6
-
-
-
6
6
max
-
15
15
7
-
-
-
7
7
max
-
20
20
9
-
-
-
9
9
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Cycle
012
Parameter
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output active from end of write
015
min
15
12
12
0
12
0
0
7
0
3
020
min
20
15
15
0
12
0
0
9
0
3
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
min
12
10
10
0
10
0
0
6
0
3
max
-
-
-
-
-
-
6
-
-
-
max
-
-
-
-
-
-
7
-
-
-
max
-
-
-
-
-
-
9
-
-
-
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
PUMA 84S32000
- 012/015/020
Issue 2.0 : March 2002
Read Cycle Timing Waveform
(1,2)
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
OH
CS
t
ACS
t
CLZ (4,5)
t
OHZ (3)
Don't
care.
Dout
Data Valid
t
CHZ (3,4,5)
AC Read Characteristics Notes
(1) WE is High for Read Cycle.
(2) All read cycle timing is referenced from the last valid address to the first transition address.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve open circuit conditions and are
not referenced to output voltage levels.
(4) At any given temperature and voltage condition, t
CHZ
(max) is less than t
CLZ
(min) both for a given module
and from module to module.
(5) These parameters are sampled and not 100% tested.
Write Cycle No.1 Timing Waveform
(1,4)
t
WC
Address
t
WR(7)
OE
t
AS(6)
t
AW
t
CW
CS
Don't
Care
WE
t
OHZ(3,9)
t
WP(2)
High-Z
t
DW
t
DH
t
OW
(8)
Dout
High-Z
Din
Data Valid
5
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