CAT25640
EEPROM Serial 64-Kb SPI
Description
The CAT25640 is a EEPROM Serial 64−Kb SPI device internally
organized as 8Kx8 bits. This features a 64−byte page write buffer and
supports the Serial Peripheral Interface (SPI) protocol. The device is
enabled through a Chip Select (CS) input. In addition, the required bus
signals are clock input (SCK), data input (SI) and data output (SO)
lines. The HOLD input may be used to pause any serial
communication with the CAT25640 device. The device features
software and hardware write protection, including partial as well as
full array protection.
Features
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SOIC−8
V SUFFIX
CASE 751BD
UDFN−8
HU4 SUFFIX
CASE 517AZ
TSSOP−8
Y SUFFIX
CASE 948AL
20 MHz (5 V) SPI Compatible
1.8 V to 5.5 V Supply Voltage Range
SPI Modes (0,0) & (1,1)
64−byte Page Write Buffer
Self−timed Write Cycle
Hardware and Software Protection
Block Write Protection
−
Protect
1
/
4
,
1
/
2
or Entire EEPROM Array
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
SOIC, TSSOP 8−lead and UDFN 8−pad Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
V
CC
PIN CONFIGURATION
CS
SO
WP
V
SS
1
V
CC
HOLD
SCK
SI
SOIC (V), TSSOP (Y), UDFN (HU4)
PIN FUNCTION
Pin Name
CS
SO
WP
V
SS
SI
SCK
Function
Chip Select
Serial Data Output
Write Protect
Ground
Serial Data Input
Serial Clock
Hold Transmission Input
Power Supply
SI
CS
WP
HOLD
SCK
CAT25640
SO
HOLD
V
CC
ORDERING INFORMATION
V
SS
See detailed ordering and shipping information in the package
dimensions section on page 13 of this data sheet.
Figure 1. Functional Symbol
©
Semiconductor Components Industries, LLC, 2012
June, 2018
−
Rev. 11
1
Publication Order Number:
CAT25640/D
CAT25640
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Operating Temperature
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
Ratings
−45
to +130
−65
to +150
−0.5
to +6.5
Units
°C
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than
−0.5
V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than
−1.5
V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
Symbol
I
CCR
I
CCW
I
SB1
I
SB2
I
L
I
LO
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Supply Current
(Read Mode)
Supply Current
(Write Mode)
Standby Current
(
V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Test Conditions
Read, V
CC
= 5.5 V,
SO open
Write, V
CC
= 5.5 V,
SO open
V
IN
= GND or V
CC
, CS = V
CC
,
WP = V
CC
, V
CC
= 5.5 V
V
IN
= GND or V
CC
, CS = V
CC
,
WP = GND, V
CC
= 5.5 V
V
IN
= GND or V
CC
CS = V
CC
,
V
OUT
= GND or V
CC
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
10 MHz /
−40°C
to 85°C
5 MHz /
−40°C
to 125°C
10 MHz /
−40°C
to 85°C
5 MHz /
−40°C
to 125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−2
−1
−1
−0.5
0.7 V
CC
V
CC
≥
2.5 V, I
OL
= 3.0 mA
V
CC
≥
2.5 V, I
OH
=
−1.6
mA
V
CC
< 2.5 V, I
OL
= 150
mA
V
CC
< 2.5 V, I
OH
=
−100
mA
V
CC
−
0.2 V
V
CC
−
0.8 V
0.2
Min
Max
2
2
3
3
1
2
3
5
2
1
2
0.3 V
CC
V
CC
+ 0.5
0.4
V
V
V
V
V
V
mA
mA
mA
mA
mA
Units
mA
Standby Current
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
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CAT25640
Table 4. D.C. OPERATING CHARACTERISTICS
−
NEW PRODUCT (Rev F)
Symbol
I
CCR
Parameter
Supply Current
(Read Mode)
Read, SO open /
−40°C
to +85°C
Test Conditions
V
CC
= 1.8 V, f
SCK
= 5 MHz
V
CC
= 2.5 V, f
SCK
=10 MHz
V
CC
= 5.5 V, f
SCK
= 20 MHz
Read, SO open /
−40°C
to +125°C
I
CCW
Supply Current
(Write Mode)
Write, CS = V
CC
/
−40°C
to +85°C
2.5 V< V
CC
< 5.5 V,
f
SCK
= 10 MHz
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 5.5 V
Write, CS = V
CC
/
−40°C
to +125°C
I
SB1
Standby Current
V
IN
= GND or V
CC
,
CS = V
CC
, WP = V
CC
,
V
CC
= 5.5 V
V
IN
= GND or V
CC
,
CS = V
CC
, WP = GND,
V
CC
= 5.5 V
V
IN
= GND or V
CC
CS = V
CC
V
OUT
= GND or V
CC
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
2.5 V< V
CC
< 5.5 V
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
T
A
=
−40°C
to +85°C
T
A
=
−40°C
to +125°C
−2
−1
−1
−0.5
0.7 V
CC
V
CC
> 2.5 V, I
OL
= 3.0 mA
V
CC
> 2.5 V, I
OH
=
−1.6
mA
V
CC
< 2.5 V, I
OL
= 150
mA
V
CC
< 2.5 V, I
OH
=
−100
mA
V
CC
−
0.2 V
V
CC
−
0.8 V
0.2
(
V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C and V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.)
Min
Max
0.2
0.3
0.6
0.6
0.8
1.4
2
2
1
3
3
5
2
1
2
0.3 V
CC
V
CC
+ 0.5
0.4
V
V
V
V
V
V
mA
mA
mA
mA
mA
Units
mA
I
SB2
Standby Current
I
L
I
LO
V
IL
V
IH
V
OL1
V
OH1
V
OL2
V
OH2
Input Leakage Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Table 5. PIN CAPACITANCE
(Note 4) (T
A
= 25°C, f = 1.0 MHz, V
CC
= +5.0 V)
Symbol
C
OUT
C
IN
Output Capacitance (SO)
Input Capacitance (CS, SCK, SI, WP, HOLD)
Test
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
8
8
Units
pF
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT25640
Table 6. A.C. CHARACTERISTICS
−
MATURE PRODUCT
(T
A
=
−40°C
to +85°C (Industrial) and T
A
=
−40°C
to +125°C (Extended).) (Notes 5, 8)
V
CC
= 1.8 V
−
5.5 V /
−405C
to +855C
V
CC
= 2.5 V
−
5.5 V /
−405C
to +1255C
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 6)
t
FI
(Note 6)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
(Note 8)
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 7)
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Interactive Setup Time
CS Interactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
50
20
30
20
20
10
100
5
0
50
100
20
15
20
15
15
10
60
5
0
10
75
0
20
25
Min
DC
40
40
75
75
50
2
2
0
10
40
Max
5
V
CC
= 2.5 V
−
5.5 V
−405C
to +855C
Min
DC
20
20
40
40
25
2
2
Max
10
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
5. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 50 pF
6. This parameter is tested initially and after a design or process change that affects the parameter.
7. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
8.
All Chip Select (CS) timing parameters are defined relative to the positive clock edge (Figure 2). t
CSH
timing specification is valid
for die revision E and higher. The die revision E is identified by letter “E” or a dedicated marking code on top of the package. For
previous product revision (Rev. D) the t
CSH
is defined relative to the negative clock edge.
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CAT25640
Table 7. A.C. CHARACTERISTICS – NEW PRODUCT (Rev F)
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +85°C (Industrial) and
V
CC
= 2.5 V to 5.5 V, T
A
=
−40°C
to +125°C, unless otherwise specified.) (Note 9)
V
CC
= 1.8 V
−
5.5 V
−405C
to +855C
Symbol
f
SCK
t
SU
t
H
t
WH
t
WL
t
LZ
t
RI
(Note 10)
t
FI
(Note 10)
t
HD
t
CD
t
V
t
HO
t
DIS
t
HZ
t
CS
t
CSS
t
CSH
t
CNS
t
CNH
t
WPS
t
WPH
t
WC
(Note 11)
Parameter
Clock Frequency
Data Setup Time
Data Hold Time
SCK High Time
SCK Low Time
HOLD to Output Low Z
Input Rise Time
Input Fall Time
HOLD Setup Time
HOLD Hold Time
Output Valid from Clock Low
Output Hold Time
Output Disable Time
HOLD to Output High Z
CS High Time
CS Setup Time
CS Hold Time
CS Inactive Setup Time
CS Inactive Hold Time
WP Setup Time
WP Hold Time
Write Cycle Time
80
30
30
20
20
10
10
5
0
50
100
40
30
30
20
20
10
10
5
0
10
70
0
20
25
20
15
20
15
15
10
10
5
Min
DC
20
20
75
75
50
2
2
0
10
35
0
20
25
Max
5
V
CC
= 2.5 V
−
5.5 V
−405C
to +1255C
Min
DC
10
10
40
40
25
2
2
0
5
20
Max
10
V
CC
= 4.5 V
−
5.5 V
−405C
to +855C
Min
DC
5
5
20
20
25
2
2
Max
20
Units
MHz
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
9. AC Test Conditions:
Input Pulse Voltages: 0.3 V
CC
to 0.7 V
CC
Input rise and fall times:
≤
10 ns
Input and output reference voltages: 0.5 V
CC
Output load: current source I
OL max
/I
OH max
; C
L
= 30 pF
10. This parameter is tested initially and after a design or process change that affects the parameter.
11. t
WC
is the time from the rising edge of CS after a valid write sequence to the end of the internal write cycle.
Table 8. POWER−UP TIMING
(Notes 10, 12)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
12. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
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