CAT5269
Dual Digitally Programmable Potentiometers
(DPP™) with 256 Taps and 2-wire Interface
FEATURES
Four linear taper digitally programmable
potentiometers
256 resistor taps per potentiometer
End to end resistance 50 kΩ or 100 kΩ
Potentiometer control and memory access via
2-wire interface (I
2
C like)
Low wiper resistance, typically 100
Ω
Nonvolatile memory storage for up to four
wiper settings for each potentiometer
Automatic recall of saved wiper settings at
power up
2.5 to 6.0 volt operation
Standby current less than 1 µA
1,000,000 nonvolatile WRITE cycles
100 year nonvolatile memory data retention
24-lead SOIC and TSSOP packages
Industrial temperature range
For Ordering Information details, see page 15.
DESCRIPTION
The CAT5269 is two digitally programmable poten–
tiometers (DPPs™) integrated with control logic and
18 bytes of NVRAM memory. Each DPP consists of a
series of resistive elements connected between two
externally accessible end points. The tap points
between each resistive element are connected to the
wiper outputs with CMOS switches. A separate 8-bit
control register (WCR) independently controls the
wiper tap switches for each DPP. Associated with
each wiper control register are four 8-bit non-volatile
memory data registers (DR) used for storing up to four
wiper settings. Writing to the wiper control register or
any of the non-volatile data registers is via a 2-wire
serial bus. On power-up, the contents of the first data
register (DR0) for each of the four potentiometers is
automatically loaded into its respective wiper control
registers.
The CAT5269 can be used as a potentiometer or as a
two terminal, variable resistor. It is intended for circuit
level or system level adjustments in a wide variety of
applications. It is available in the -40ºC to 85ºC
industrial operating temperature ranges and offered in
a 24-lead SOIC and TSSOP package.
FUNCTIONAL DIAGRAM
PIN CONFIGURATION
SOIC (W)
TSSOP (Y)
NC
A0
NC
NC
NC
NC
V
CC
R
LO
R
HO
1
2
3
4
5
6
7
8
9
24 A3
23 SCL
22 NC
21 NC
20 NC
19 NC
18 GND
17 R
W1
16 R
H1
15 R
L1
14 A1
13 SDA
WP
A0
A1
A2
A3
CONTROL
LOGIC
NONVOLATILE
DATA
REGISTERS
R
L0
R
L1
R
W1
SCL
SDA
2-WIRE BUS
INTERFACE
WIPER
CONTROL
REGISTERS
R
H0
R
H1
R
W0
R
WO
10
A2 11
¯¯¯ 12
WP
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
1
Doc. No. MD-2123 Rev. F
CAT5269
PIN DESCRIPTIONS
SCL: Serial Clock
The CAT5269 serial clock input pin is used to
clock all data transfers into or out of the
device.
SDA: Serial Data
The CAT5269 bidirectional serial data pin is
used to transfer data into and out of the
device. The SDA pin is an open drain output
and can be wire-Ored with the other open
drain or open collector I/Os.
A0, A1, A2, A3: Device Address Inputs
These inputs set the device address when
addressing multiple devices. A total of sixteen
devices can be addressed on a single bus. A
match in the slave address must be made with
the address input in order to initiate
communication with the CAT5269.
R
H
, R
L
: Resistor End Points
The two sets of R
H
and R
L
pins are equivalent
to the terminal connections on a mechanical
potentiometer.
R
W
: Wiper
The R
W
pins are equivalent to the wiper
terminal of a mechanical potentiometer.
¯¯¯: Write Protect Input
WP
The ¯¯¯ pin when tied low prevents non-
WP
volatile writes to the data register (change of
wiper control register is allowed) and when
tied high or left floating normal read/write
operations are allowed. See Write Protection
on page 7 for more details.
PIN DESCRIPTION
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Name
NC
A0
NC
NC
NC
NC
V
CC
R
L0
R
H0
R
W0
A2
¯¯¯
WP
SDA
A1
R
L1
R
H1
R
W1
GND
NC
NC
NC
NC
SCL
A3
Function
No Connect
Device Address, LSB
No Connect
No Connect
No Connect
No Connect
Supply Voltage
Low Reference Terminal for Potentiometer 0
High Reference Terminal for Potentiometer 0
Wiper Terminal for Potentiometer 0
Device Address
Write Protection
Serial Data Input/Output
Device Address
Low Reference Terminal for Potentiometer 1
High Reference Terminal for Potentiometer 1
Wiper Terminal for Potentiometer 1
Ground
No Connect
No Connect
No Connect
No Connect
Bus Serial Clock
Device Address
DEVICE OPERATION
The CAT5269 is two resistor arrays integrated with a 2-wire serial interface, two 8-bit wiper control registers and
eight 8-bit, non-volatile memory data registers. Each resistor array contains 255 separate resistive elements
connected in series. The physical ends of each array are equivalent to the fixed terminals of a mechanical
potentiometer (R
H
and R
L
). The tap positions between and at the ends of the series resistors are connected to the
output wiper terminals (R
W
) by a CMOS transistor switch. Only one tap point for each potentiometer is connected
to its wiper terminal at a time and is determined by the value of the wiper control register. Data can be read or
written to the wiper control registers or the non-volatile memory data registers via the 2-wire bus. Additional
instructions allow data to be transferred between the wiper control registers and each respective potentiometer's
non-volatile data registers. Also, the device can be instructed to operate in an "increment/decrement" mode.
Doc. No. MD-2123 Rev. F
2
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5269
ABSOLUTE MAXIMUM RATINGS
(1)
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to V
SS(1) (2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25ºC)
Lead Soldering Temperature (10 s)
Wiper Current
RECOMMENDED OPERATING CONDITIONS
Parameters
V
CC
Industrial Temperature
POTENTIOMETER CHARACTERISTICS
(Over recommended operating conditions unless otherwise stated.)
Symbol
R
POT
R
POT
Parameter
Potentiometer Resistance (100 kΩ)
Potentiometer Resistance (50 kΩ)
Potentiometer Resistance
Tolerance
R
POT
Matching
Power Rating
Wiper Current
Wiper Resistance
Wiper Resistance
Voltage on any R
H
or R
L
Pin
Resolution
Absolute Linearity
(5)
Relative Linearity
(6)
Temperature Coefficient of R
POT
Ratiometric Temp. Coefficient
Potentiometer Capacitances
Frequency Response
Test Conditions
Min
Limits
Typ.
100
50
Max
Units
kΩ
kΩ
±20
25°C, each pot
I
W
= ±3 mA @ V
CC
= 3 V
I
W
= ±3 mA @ V
CC
= 5 V
V
SS
= 0 V
R
w(n)(actual)
-R
(n)(expected)(8)
R
w(n+1)
-[R
w(n)+LSB](8)
(4)
(4)
(4)
R
POT
= 50 kΩ
(4)
±300
20
10/10/25
0.4
200
100
V
SS
0.4
±1
±0.2
1
50
±3
300
150
V
CC
%
%
mW
mA
Ω
Ω
V
%
LSB
(7)
LSB
(7)
ppm/ºC
ppm/ºC
pF
MHz
Ratings
+2.5 to +6
-40 to +85
Units
V
°C
Ratings
-55 to +125
-65 to +150
-2.0 to +V
CC
+ 2.0
-2.0 to +7.0
1.0
300
±6
Units
ºC
°C
V
V
W
ºC
mA
I
W
R
W
R
W
V
TERM
TC
RPOT
TC
RATIO
C
H
/C
L
/C
W
fc
Notes:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this
specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The minimum DC input voltage is –0.5 V. During transitions, inputs may undershoot to –2.0 V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5 V, which may overshoot to V
CC
+2.0 V for periods of less than 20 ns.
(3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1 V to V
CC
+1 V.
(4) This parameter is tested initially and after a design or process change that affects the parameter.
(5) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a potentiometer.
(6) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentio-
meter. It is a measure of the error in step size.
(7) LSB = R
TOT
/ 255 or (R
H
- R
L
) / 255, single pot
(8) n = 0, 1, 2, ..., 255
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
3
Doc. No. MD-2123 Rev. F
CAT5269
D.C. OPERATING CHARACTERISTICS
V
CC
= +2.5 V to +6.0 V, unless otherwise specified.
Symbol
I
CC1
I
CC2
I
SB
I
LI
I
LO
V
IL
V
IH
V
OL1
Parameter
Power Supply Current
Power Supply Current
Non-volatile WRITE
Standby Current (V
CC
= 5 V)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Output Low Voltage (V
CC
= 3 V)
I
OL
= 3 mA
Test Conditions
f
SCL
= 400 kHz, SDA = Open
V
CC
= 6 V, Inputs = GND
f
SCK
= 400 kHz, SDA Open
V
CC
= 6 V, Input = GND
V
IN
= GND or V
CC
, SDA = Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
-1
V
CC
x 0.7
Min
Max
1
5
5
10
10
V
CC
x 0.3
V
CC
+ 1.0
0.4
Units
mA
mA
µA
µA
µA
V
V
V
CAPACITANCE
T
A
= 25ºC, f = 1.0 MHz, V
CC
= 5 V
Symbol
C
I/O(1)
C
IN(1)
Test
Input/Output Capacitance (SDA)
Input Capacitance (A0, A1, A2, A3, SCL, ¯¯¯)
WP
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
A.C. CHARACTERISTICS
2.5V - 6.0V
Symbol
f
SCL
T
I(1)
t
AA
t
BUF(1)
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
(1)
Parameter
Clock Frequency
Noise Suppression Time Constant at SCL, SDA Inputs
SLC Low to SDA Data Out and ACK Out
Time the bus must be free before a new transmission can start
Start Condition Hold Time
Clock Low Period
Clock High Period
Start Condition Setup Time (for a Repeated Start Condition)
Data in Hold Time
Data in Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Min
Max
400
200
1
Units
kHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
1.2
0.6
1.2
0.6
0.6
0
50
0.3
300
0.6
100
µs
ns
µs
ns
t
F(1)
t
SU:STO
t
DH
Note:
This parameter is tested initially and after a design or process change that affects the parameter.
Doc. No. MD-2123 Rev. F
4
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
CAT5269
POWER UP TIMING
(1)(2)
Symbol
t
PUR
t
PUW
Parameter
Power-up to Read Operation
Power-up to Write Operation
Max
1
1
Units
ms
ms
WIPER TIMING
Symbol
t
WRPO
t
WRL
Parameter
Wiper Response Time After Power Supply Stable
Wiper Response Time After Instruction Issued
Max
10
10
Units
µs
µs
WRITE CYCLE LIMITS
(3)
Symbol
t
WR
Parameter
Write Cycle Time
Max
5
Units
ms
RELIABILITY CHARACTERISTICS
Symbol
N
END
(1)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Reference Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
V
mA
T
DR(1)
V
ZAP(1)
I
LTH(1)
Notes:
(1)
(2)
(3)
This parameter is tested initially and after a design or process change that affects the parameter.
t
PUR
and t
PUW
are delays required from the time V
CC
is stable until the specified operation can be initiated.
The write cycle is the time from a valid stop condition of a write sequence to the end of the internal program/erase cycle. During the write
cycle, the bus interface circuits are disabled, SDA is allowed to remain high, and the device does not respond to its slave address.
Figure 1. Bus Timing
tF
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT
tSU:STO
tHIGH
tLOW
tR
SDA IN
tAA
SDA OUT
tDH
tBUF
© 2009 SCILLC. All rights reserved.
Characteristics subject to change without notice
5
Doc. No. MD-2123 Rev. F
ARM技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
