Intel
®
LXT971A
3.3V Dual-Speed Fast Ethernet PHY Transceiver
Datasheet
The LXT971A is an IEEE compliant Fast Ethernet PHY Transceiver that directly supports both
100BASE-TX and 10BASE-T applications. It provides a Media Independent Interface (MII) for
easy attachment to 10/100 Media Access Controllers (MACs). The LXT971A also provides a
Low Voltage PECL (LVPECL) interface for use with 100BASE-FX fiber networks.
This document also supports the LXT971 device.
The LXT971A supports full-duplex operation at 10 Mbps and 100 Mbps. Its operating condition
can be set using auto-negotiation, parallel detection, or manual control.
The LXT971A is fabricated with an advanced CMOS process and requires only a single 3.3V
power supply.
Applications
■
Combination 10BASE-T/100BASE-TX or
100BASE-FX Network Interface Cards
(NICs)
■
■
10/100 PCMCIA Cards
Cable Modems and Set-Top Boxes
Product Features
■
■
■
■
■
■
■
■
■
■
3.3V Operation.
Low power consumption (300 mW
typical).
Low-power “Sleep” mode.
10BASE-T and 100BASE-TX using a
single RJ-45 connection.
Supports auto-negotiation and parallel
detection.
MII interface with extended register
capability.
Robust baseline wander correction
performance.
100BASE-FX fiber-optic capable.
Standard CSMA/CD or full-duplex
operation.
Supports JTAG boundary scan.
■
■
■
■
Configurable via MDIO serial port or
hardware control pins.
Integrated, programmable LED drivers.
64-ball Plastic Ball Grid Array (PBGA).
— LXT971ABC - Commercial (0
°
to
70
°
C ambient).
— LXT971ABE - Extended (-40
°
to 85
°
C
ambient).
64-pin Low-profile Quad Flat Package
(LQFP).
— LXT971ALC - Commercial (0
°
to
70
°
C ambient).
— LXT971ALE - Extended (-40
°
to 85
°
C
ambient).
Order Number: 249414-002
August 2002
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTELÆ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY
ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S
TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY
EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES
RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER
INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition
and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
The LXT971A may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized
errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 2002
*Third-party brands and names are the property of their respective owners.
2
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Contents
1.0
2.0
3.0
Pin Assignments ..............................................................................................................................12
Signal Descriptions ..........................................................................................................................16
Functional Description.....................................................................................................................21
3.1
Introduction .......................................................................................................................21
3.1.1
Comprehensive Functionality .............................................................................21
3.1.2
OSP™ Architecture ............................................................................................21
Network Media / Protocol Support....................................................................................22
3.2.1
10/100 Network Interface ...................................................................................22
3.2.1.1 Twisted-Pair Interface ..........................................................................22
3.2.1.2 Fiber Interface.......................................................................................22
3.2.1.3 Fault Detection and Reporting..............................................................23
3.2.2
MII Data Interface...............................................................................................23
3.2.2.1 Increased MII Drive Strength ...............................................................23
3.2.3
Configuration Management Interface .................................................................24
3.2.3.1 MDIO Management Interface ..............................................................24
3.2.3.2 Hardware Control Interface ..................................................................25
Operating Requirements....................................................................................................26
3.3.1
Power Requirements ...........................................................................................26
3.3.2
Clock Requirements............................................................................................26
3.3.2.1 External Crystal/Oscillator ...................................................................26
3.3.2.2 MDIO Clock .........................................................................................26
Initialization.......................................................................................................................26
3.4.1
MDIO Control Mode ..........................................................................................26
3.4.2
Hardware Control Mode .....................................................................................27
3.4.3
Reduced Power Modes........................................................................................28
3.4.3.1 Hardware Power Down ........................................................................28
3.4.3.2 Software Power Down..........................................................................29
3.4.3.3 Sleep Mode ...........................................................................................29
3.4.4
Reset....................................................................................................................29
3.4.5
Hardware Configuration Settings........................................................................30
Establishing Link...............................................................................................................31
3.5.1
Auto-Negotiation ................................................................................................31
3.5.1.1 Base Page Exchange .............................................................................31
3.5.1.2 Next Page Exchange .............................................................................31
3.5.1.3 Controlling Auto-Negotiation...............................................................31
3.5.2
Parallel Detection ................................................................................................31
MII Operation....................................................................................................................32
3.6.1
MII Clocks ..........................................................................................................32
3.6.2
Transmit Enable ..................................................................................................33
3.6.3
Receive Data Valid .............................................................................................33
3.6.4
Carrier Sense .......................................................................................................33
3.6.5
Error Signals .......................................................................................................33
3.6.6
Collision ..............................................................................................................33
3.6.7
Loopback.............................................................................................................34
3.6.7.1 Operational Loopback ..........................................................................35
3.2
3.3
3.4
3.5
3.6
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
3
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
3.7
3.8
3.9
3.10
3.6.7.2 Test Loopback...................................................................................... 35
100 Mbps Operation ......................................................................................................... 36
3.7.1
100BASE-X Network Operations...................................................................... 36
3.7.2
Collision Indication ............................................................................................ 38
3.7.3
100BASE-X Protocol Sublayer Operations ....................................................... 38
3.7.3.1 PCS Sublayer ....................................................................................... 38
3.7.3.2 PMA Sublayer...................................................................................... 41
3.7.3.3 Twisted-Pair PMD Sublayer ................................................................ 42
3.7.3.4 Fiber PMD Sublayer ............................................................................ 43
10 Mbps Operation ........................................................................................................... 43
3.8.1
10BASE-T Preamble Handling.......................................................................... 43
3.8.2
10BASE-T Carrier Sense ................................................................................... 43
3.8.3
10BASE-T Dribble Bits ..................................................................................... 43
3.8.4
10BASE-T Link Integrity Test........................................................................... 44
3.8.4.1 Link Failure.......................................................................................... 44
3.8.5
10BASE-T SQE (Heartbeat) .............................................................................. 44
3.8.6
10BASE-T Jabber .............................................................................................. 44
3.8.7
10BASE-T Polarity Correction .......................................................................... 44
Monitoring Operations ..................................................................................................... 44
3.9.1
Monitoring Auto-Negotiation ............................................................................ 44
3.9.1.1 Monitoring Next Page Exchange......................................................... 45
3.9.2
LED Functions ................................................................................................... 45
3.9.2.1 LED Pulse Stretching........................................................................... 45
Boundary Scan (JTAG1149.1) Functions ........................................................................ 46
3.10.1 Boundary Scan Interface .................................................................................... 46
3.10.2 State Machine..................................................................................................... 46
3.10.3 Instruction Register ............................................................................................ 46
3.10.4 Boundary Scan Register (BSR).......................................................................... 46
Magnetics Information ..................................................................................................... 48
Typical Twisted-Pair Interface ......................................................................................... 48
The Fiber Interface ........................................................................................................... 52
Electrical Parameters ........................................................................................................ 56
Timing Diagrams .............................................................................................................. 61
4.0
Application Information.................................................................................................................. 48
4.1
4.2
4.3
5.0
Test Specifications .......................................................................................................................... 56
5.1
5.2
6.0
7.0
8.0
Register Definitions ........................................................................................................................ 71
Package Specifications.................................................................................................................... 88
Product Ordering Information......................................................................................................... 90
4
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
LXT971A 3.3 V Dual-Speed Fast Ethernet Transceiver
Figures
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
LXT971A Block Diagram...................................................................................................9
64-Pin PBGA Pin Assignments.........................................................................................10
64-Pin LQFP Pin Assignments..........................................................................................11
Management Interface Read Frame Structure...................................................................21
Management Interface Write Frame Structure ..................................................................21
Interrupt Logic...................................................................................................................22
Initialization Sequence ......................................................................................................24
Hardware Configuration Settings ......................................................................................26
Link Establishment Overview ...........................................................................................28
10BASE-T Clocking .........................................................................................................30
100BASE-X Clocking .......................................................................................................30
Link Down Clock Transition.............................................................................................30
Loopback Paths .................................................................................................................31
100BASE-X Frame Format...............................................................................................32
100BASE-TX Data Path....................................................................................................33
100BASE-TX Reception with no Errors...........................................................................33
100BASE-TX Reception with Invalid Symbol .................................................................33
100BASE-TX Transmission with no Errors......................................................................34
100BASE-TX Transmission with Collision......................................................................34
Protocol Sublayers.............................................................................................................35
LED Pulse Stretching ........................................................................................................42
Typical Twisted-Pair Interface - Switch............................................................................45
Typical Twisted-Pair Interface - NIC................................................................................46
Typical MII Interface ........................................................................................................47
Typical Fiber Interface ......................................................................................................48
100BASE-TX Receive Timing - 4B Mode .......................................................................53
100BASE-TX Transmit Timing - 4B Mode......................................................................54
100BASE-FX Receive Timing..........................................................................................55
100BASE-FX Transmit Timing ........................................................................................56
10BASE-T Receive Timing ..............................................................................................57
10BASE-T Transmit Timing.............................................................................................58
10BASE-T Jabber and Unjabber Timing ..........................................................................59
10BASE-T SQE (Heartbeat) Timing.................................................................................59
Auto Negotiation and Fast Link Pulse Timing..................................................................60
Fast Link Pulse Timing .....................................................................................................60
MDIO Input Timing ..........................................................................................................61
MDIO Output Timing........................................................................................................61
Power-Up Timing..............................................................................................................62
RESET Pulse Width and Recovery Timing ......................................................................62
PHY Identifier Bit Mapping..............................................................................................68
PBGA Package Specification ............................................................................................79
LXT971A LQFP Package Specifications..........................................................................80
Datasheet
Document #: 249414
Revision #: 002
Rev. Date: August 7, 2002
5
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