an Intel company
1.244 GHz
Generic PLL
Clock
Synthesiser
GD16590
Preliminary
Features
As an option the GD16590 may be oper-
ated with an external Voltage Controlled
Crystal Oscillator for applications de-
manding a high-Q oscillator.
The reference clock may range from 19
to 622 MHz.
The GD16590 requires a single +3.3 V
power supply.
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General Information
The GD16590 is a generic PLL clock
synthesiser. The device targets clock dis-
tribution in SDH/SONET telecommunica-
tion systems but is well suited for a wide
range of applications requiring high per-
formance high-speed clock synthesis.
The device implements a fully integrated
multiplying PLL including:
u
An on-chip Voltage Controlled
Oscillator (VCO)
u
Phase-Frequency Detector
u
Programmable frequency dividers
(prescalers).
The loop-filter is external in order to opti-
mise the PLL for different applications.
Six separate differential clock outputs
from the PLL at :
1,244.16 / 622.08 MHz
1,244.16 / 622.08 MHz
622.08 / 311.04 MHz
311.04 / 155.52 MHz
155.52 / 77.76 MHz
77.76 / 38.88 MHz
all with separate enable.
Three independent selectable
reference clock inputs.
Intrinsic jitter: 0.005 UI
PP
@ 622 MHz.
Low phase skew between output
clocks: < 200 ps.
Optional external VCXO possible.
Simple external loop filter.
Lock detect output signal.
Single power supply: +3.3 V.
Low power operation: 0.54 W (Typ.).
Package: 48 pin TQFP (7 × 7 mm).
The device is housed in a 48 TQFP
7 × 7 mm thermally enhanced package.
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VCXO
R1
C1
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×3
CKREFx
CKRTx
CKREFxN
50R
50R
V
R
D
U
OCHP
VCTL
DCCAL
VCXO
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Select
CHAP
VCO
2.5 GHz
3:1
PFC
Div.
2, 4
/2
VCCA
VCC
VEE
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XOR
SEL1
SEL2
CHAP
Select
4:1
VCOSEL1
VCOSEL2
NLDET
C2
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Div.
1, 2,
4, 8, 16,
32, 64
×7
Select
NLOCK
×6
OUTENAx
FOUTx
FOUTxN
Applications
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7:1
×7
×3
Tele Communications systems:
– SDH
– SONET
Datacom
High-speed general clock distribution.
×3
SEL3/4/5
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Data Sheet Rev.: 13
Functional Details
The GD16590 comprises:
u
a low-noise LC-type VCO
u
a Phase-Frequency Detector
u
frequency dividers (prescalers)
u
a charge pump
into an integrated PLL frequency
synthesiser. Careful design and layout
matching ensures short delay and mini-
mum skew between input reference
clocks and outputs.
NLDET
C2
F
REF
F
VAR
10nF
R
U
NLOCK
PFD
V
D
Jitter Performance
The frequency of the input reference
clock may range between 19.44 MHz
and 622.08 MHz. Since changing the ref-
erence frequency alters the loop-gain
within the PLL it may be necessary to ad-
just the loop-filter components when
switching to a different reference fre-
quency in order to achieve ITU-T recom-
mended performance.
CHAP
VCO
OCHP
R1
C1
1kW
1
m
F
VCTL
VCCA
+3.3V
PLL Propagation Delay
When the PLL is in lock the Phase Fre-
quency Detector aligns the positive (low
to high transition) flanks of the reference
clock and divided VCO clock on it’s in-
puts. These inputs are marked R and V
on the Figure 1. This means the positive
transition of any FOUTx output clock is
aligned with the positive transition of the
reference clock under the condition of
equal reference clock frequency and
FOUTx output frequency, please refer to
Figure 7. Figure 7 defines the PLL propa-
gation delay parameter (D
OUT
) that is the
skew between the reference clock and
output clock when the loop is locked.
Note that
D
OUT
will change with leakage
currents drawn from the loop-filter, hence
D
OUT
is loop-filter dependant.
Figure 9 shows a measurement of
D
OUT
.
The CKREF1 input signal is shown to-
gether with the FOUTA output signal,
both running 622 MHz with the PLL
locked using the recommended loop-filter
and no excessive leakage current drawn
from the charge pump output. A skew of
approximately 80 ps was observed. The
skew has been investigated over supply
and temperature and was observed as
less than 200 ps at any combination of
extremes. The observations are only
valid with the PLL locked when using the
recommended loop-filter.
Figure 10 illustrates the phase relation-
ship when a 155 MHz clock is input at
CKREF1 and the FOUTA output is run-
ning at 622 MHz. Note the asymmetric
reference clock.
VCCA
Figure 1.
Application diagram.
Output Clocks
The GD16590 is equipped with six
LVPECL compatible output buffers. Each
of the output buffers is equipped with an
LVTTL enable pin that may be used to
disable clock signals not in use for noise
reduction. The phases of the clock output
signals are aligned with less than 200 ps
skew peak-to-peak between any two
clock signals. Available clocks signals
from the PLL are divide by 1 (signal
FOUTA and by FOUTB), divide by 2
(FOUT2), divide by 4 (FOUT4), divide by
8 (FOUT8) and divide by 16 (FOUT16).
first-order RC-circuit as shown on
Fig-
ure 1,
resulting in a second order, type 2
loop.
The values of R and C depend on the ap-
plication. With respect to ITU-T recom-
mended jitter performance appropriate
values for R and C have been deter-
mined to R = 1 kW and C = 1
mF.
The values ensures stable operation with
reference clock ranging from 19 MHz to
622 MHz. Note that the loop-filter should
be terminated to the positive VCO sup-
ply. An external VCXO might require a
different termination point for lowest
point.
Lock Detect
The device outputs a signal NLDET that
may be used to signal whether or not the
PLL is locked thus allowing fault diagnos-
tics. The NLDET outputs the result of an
XOR operation on the signals input to the
phase-frequency detector. To be useful
this signal must be filtered by a capacitor.
The recommended value of this capacitor
is 10 nF. The filtered lock-detect signal is
output as an LVTTL compatible signal on
the output NLOCK via a comparator.
Charge Pump Polarity
When the PLL increases the VCO fre-
quency, the charge pump pin OCHP
sinks current. That is, the voltage on the
loop- filter capacitor drops to increase the
oscillator frequency. So be aware, that
an external VCO must have a negative
VCO constant in order to achieve a sta-
ble lock.
On-chip VCO Power Down
When operated with an external VCXO
the on-chip VCO should be powered
down for noise reduction. This is done by
leaving VCCA open.
PLL Loop-filter
It has been chosen to locate the passive
loop-filter components externally to the
device. This allows for easy optimisation
of the loop-filter to different applications.
The recommended loop-filter is a simple
Data Sheet Rev.: 13
GD16590
Page 2 of 12
VCO source and corresponding
VCOSEL1, - 2 settings
Internal VCO
Ext. VCO: 1,244 MHz
Ext. VCO: 622 MHz
Internal VCO
Ext. VCO: 2,488 MHz
Ext. VCO: 1,244 MHz
Table 1.
0,1
0,0
1,1
1,0
0,0
1,1
FOUTA
[MHz]
622
Input reference frequency (CKREFx [MHz]) and corresponding SEL3, -4, -5 settings
0,0,0
622
N.A.
(1.244)
0,0,1
311
0,1,0
155
0,1,1
78
1,0,0
39
1,0,1
19
1,1,0
N.A.
(9.7)
19
1,1,1
Disable
Feedback
1,244
622
311
155
78
39
Input reference frequencies as function of SEL3/4/5 settings.
Prescaler Settings
For the PLL to achieve lock a proper re-
lation must exist between the input refer-
ence frequency and the setting of the
on-chip prescalers. The prescalers are
set by signals: VCOSEL1, VCOSEL2,
SEL3, SEL4, and SEL5 (refer to Table
1).
First, determine the desired master out-
put frequency. This is the frequency of
output clock FOUTA (FOUTA is mirrored
by FOUTB). Next, select whether the os-
cillator is external or internal. The VCO
source can be external (622, 1244 or
2488 MHz) or internal (2488 MHz). The
Table 1 gives the value of VCOSEL1/2.
Finally, the proper relation between the
reference clock frequency and the setting
of SEL3, SEL4, SEL5 is read from the
Table 1.
Duty Cycle Calibration
When operated with an external oscillator
the differential LVPECL inputs (VCXO
and DCCAL) are to be used. In single-
ended operation the duty cycle of the
outputs FOUTA and FOUTB may be ad-
justed by tuning the voltage on DCCAL.
Data Sheet Rev.: 13
GD16590
Page 3 of 12
Practical Considerations
When designing the PCB it is important
to consider noise issues. De-coupling ca-
pacitors should be applied to each supply
pin. Output clock lines must be routed as
transmission lines.
The reference clock inputs are termi-
nated on-chip by 50
W
to the positive
supply. Refer to
Figure 3.
The termina-
tion pins CKRT1..3 are biased on-chip to
2 V. The input impedance seen into
CKRT1..3 equals 1 kW.
The LVPECL clock outputs are termi-
nated according to
Figures 4
and
5.
Note:
Unused clock outputs must be
disabled or properly termi-
nated.
CKREFx
VCC
1.5kW
CKRTx
2.5kW
CKREFxN
VEE
50W
50W
Figure 3.
Termination of CKREFx pins.
Output
LVPECL
100nF
50W
Input
LVPECL
LVTTL select pins are terminated on-chip
with a 16 kW pull-up resistor giving a
logic “1" when not connected.
When more than two clock outputs are
used the heatsink must be connected to
the positive power supply. In any case it
is recommended to solder the heatsink
onto a VCC power plane.
100nF
50W
180W
0V
(VEE)
180W
50W
50W
2V
(VCC -1.3V)
Figure 4.
LVPECL Output Termination, AC-coupled.
VCC
16kW
LVTTL
Output
LVPECL
50W
Input
LVPECL
50W
VEE
Figure 2.
LVTTL select pin.
50W
50W
1.3V
(VCC -2V)
Figure 5.
LVPECL Output Termination, DC-coupled.
Data Sheet Rev.: 13
GD16590
Page 4 of 12
Pin List
Mnemonic:
CKREF1
CKREF1N
CKRT1
CKREF2
CKREF2N
CKRT2
CKREF3
CKREF3N
CKRT3
SEL1, SEL2
Pin No.:
2
3
4
6
7
5
10
11
9
8, 14
Pin Type:
LVPECL IN
Description:
Differential. One of three reference inputs. The input frequency is de-
pending on the mode of operation, Maximum 670 MHz. CKRT1 is the
common termination point of 2 × 50
W
resistors, internally biased to
2 V. Z
IN,CKRT1
= 1 kW.
Differential. One of three reference inputs. The input frequency is de-
pending on the mode of operation, Maximum 670 MHz. CKRT2 is the
common termination point of 2 × 50
W
resistors, internally biased to
2 V. Z
IN,CKRT2
= 1 kW
Differential. One of three reference inputs. The input frequency is de-
pending on the mode of operation, Maximum 670 MHz. CKRT3 is the
common termination point of 2 × 50
W
resistors, internally biased to
2 V. Z
IN,CKRT3
= 1 kW
.
Select for input reference clock.
The pins are equipped with 16 kW pull-up resistors.
SEL1 SEL2
0
0
CKREF1
0
1
CKREF2
1
0
CKREF3
1
1
No input reference to PLL (default)
Select for prescaler.
The pins are equipped with 16 kW pull-up resistors.
SEL3 SEL4
SEL5
0
0
0
Divide by 1 (CKREF
NOM
= 622 MHz)
0
0
1
Divide by 2 (CKREF
NOM
= 622 / 311 MHz)
0
1
0
Divide by 4 (CKREF
NOM
= 311 / 155 MHz)
0
1
1
Divide by 8 (CKREF
NOM
= 155 / 78 MHz)
1
0
0
Divide by 16 (CKREF
NOM
= 78 / 39 MHz)
1
0
1
Divide by 32 (CKREF
NOM
= 39 / 19 MHz)
1
1
0
Divide by 64 (CKREF
NOM
= 19 MHz)
1
1
1
No feed back to PLL from VCO (default)
Select for internal or external oscillator and prescale.
The pins are equipped with 16 kW pull-up resistors.
VCOSEL1
VCOSEL2
0
0
External VCXO, divide by 2,
(F
MAX
= 2.7 GHz)
0
1
Internal VCO, F
NOM
= 622 MHz
1
0
Internal VCO, F
NOM
= 1.244 MHz
1
1
External VCXO, divide by 1
(F
MAX
= 1.35 GHz) (default)
Differential external clock input, F
MAX
= 2.7 GHz / 1.35 GHz.
The input can be used differentially or the DCCAL input may be used
as a VCXO duty cycle control.
When selecting external VCXO (divide by 1) the Duty cycle of the
FOUTA/B, FOUTA/BN outputs can be controlled by DCCAL.
Adjust range: 40/60 .. 60/40 assuming sinusoidal input at VCXO.
DCCAL is connected to the inverted input.
For detalis regarding ESD, please refer to Note 2 on
page 7.
Output enable. The pins are equipped with 16 kW pull-up resistors.
When set to “1” (default), the FOUTx output is enabled. When set to
“0”, the FOUTx output is disabled. Disabled implies a fixed logic “0" at
the output. When disabled the output will be active with respect to
DC.
LVPECL OUT
Differential clock outputs from PLL.
F
FOUTA, NOM
=
1244 / 622 MHz
F
FOUTB, NOM
=
1244 / 622 MHz
F
FOUT2, NOM
=
622 / 311 MHz
F
FOUT4, NOM
=
311 / 155 MHz
F
FOUT8, NOM
=
155 / 78 MHz
F
FOUT16, NOM
=
78 / 39 MHz
Voltage control pin for internal VCO. To be connected to the loop-fil-
ter.
GD16590
Page 5 of 12
LVPECL IN
LVPECL IN
LVT IN
SEL3, SEL4, SEL5
41, 44, 45
LVT IN
VCOSEL1,
VCOSEL2
35
38
LVT IN
VCXO, DCCAL
40, 39
LVPECL IN
OUTENAA
OUTENAB
OUTENA2
OUTENA4
OUTENA8
OUTENA16
FOUTA, FOUTAN
FOUTB, FOUTBN
FOUT2, FOUT2N
FOUT4, FOUT4N
FOUT8, FOUT8N
FOUT16, FOUT16N
VCTL
32
29
26
21
18
15
34, 33
31, 30
28, 27
23, 22
20, 19
17, 16
47
LVT IN
Analog IN
Data Sheet Rev.: 13
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