HC05SB7GRS/H
REV 2.1
68HC05SB7
68HC705SB7
SPECIFICATION
(General Release)
August 27, 1998
Consumer Systems Group
Semiconductor Products Sector
Motorola reserves the right to make changes without further notice to any products herein
to improve reliability, function or design. Motorola does not assume any liability arising out
of the application or use of any product or circuit described herein; neither does it convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any
other application in which the failure of the Motorola product could create a situation
where personal injury or death may occur. Should Buyer purchase or use Motorola
products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney
fees arising out of, directly or indirectly, any claim of personal injury or death associated
with such unintended or unauthorized use, even if such claim alleges that Motorola was
negligent regarding the design or manufacture of the part.
©
Motorola, Inc., 1998
August 27, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
SECTION 1
GENERAL DESCRIPTION
1.1
FEATURES ...................................................................................................... 1-1
1.2
MASK OPTION ................................................................................................ 1-2
1.3
PEPROM FACTORY PREPROGRAMMED OPTIONS ................................... 1-2
1.4
MCU STRUCTURE.......................................................................................... 1-2
1.5
PIN ASSIGNMENTS ........................................................................................ 1-4
1.6
FUNCTIONAL PIN DESCRIPTION.................................................................. 1-4
1.6.1
VDD, VSS .................................................................................................... 1-4
1.6.2
OSC1, OSC2 ............................................................................................... 1-4
1.6.3
IRQ/VPP ...................................................................................................... 1-5
1.6.4
RESET......................................................................................................... 1-6
1.6.5
CSA ............................................................................................................. 1-6
1.6.6
TM................................................................................................................ 1-6
1.6.7
VM ............................................................................................................... 1-6
1.6.8
CAP (ADC) .................................................................................................. 1-6
1.6.9
ESV.............................................................................................................. 1-7
1.6.10 PA0-PA7 / PWM0-PWM3, SCL0-SCL1, SDA0-SDA1 ................................. 1-7
1.6.11 PB1-PB7 / TCAP, CS0-CS1, AN0-AN3 ....................................................... 1-7
1.6.12 PC4-PC7...................................................................................................... 1-7
SECTION 2
MEMORY
2.1
2.2
2.3
2.4
2.5
MEMORY MAP ................................................................................................ 2-1
INPUT/OUTPUT SECTION.............................................................................. 2-2
INTERRUPT VECTOR MAPPING ................................................................... 2-6
ROM................................................................................................................. 2-6
RAM ................................................................................................................. 2-6
SECTION 3
CENTRAL PROCESSING UNIT
3.1
3.2
3.3
3.4
3.5
3.6
3.6.1
3.6.2
3.6.3
3.6.4
3.6.5
REGISTERS .................................................................................................... 3-1
ACCUMULATOR (A)........................................................................................ 3-2
INDEX REGISTER (X) ..................................................................................... 3-2
STACK POINTER (SP) .................................................................................... 3-2
PROGRAM COUNTER (PC) ........................................................................... 3-2
CONDITION CODE REGISTER (CCR) ........................................................... 3-3
Half Carry Bit (H-Bit) .................................................................................... 3-3
Interrupt Mask (I-Bit) .................................................................................... 3-3
Negative Bit (N-Bit) ...................................................................................... 3-3
Zero Bit (Z-Bit) ............................................................................................. 3-3
Carry/Borrow Bit (C-Bit) ............................................................................... 3-4
MOTOROLA
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MC68HC05SB7
REV 2.1
GENERAL RELEASE SPECIFICATION
August 27, 1998
TABLE OF CONTENTS
Section
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
4.4.1
4.4.2
4.5
4.5.1
4.5.2
4.6
4.6.1
4.6.2
4.6.3
4.7
4.8
4.8.1
4.8.2
4.9
INTERRUPT VECTORS .................................................................................. 4-1
INTERRUPT PROCESSING............................................................................ 4-2
SOFTWARE INTERRUPT ............................................................................... 4-4
EXTERNAL INTERRUPT................................................................................. 4-4
IRQ/VPP Pin ................................................................................................ 4-4
IRQ Status and Control Register (ISCR) ..................................................... 4-5
CORE TIMER INTERRUPTS........................................................................... 4-6
Core Timer Overflow Interrupt ..................................................................... 4-7
Real-Time Interrupt...................................................................................... 4-7
PROGRAMMABLE TIMER INTERRUPTS ...................................................... 4-7
Input Capture Interrupt................................................................................. 4-7
Output Compare Interrupt............................................................................ 4-7
Timer Overflow Interrupt .............................................................................. 4-7
SM-BUS INTERRUPT...................................................................................... 4-8
ANALOG INTERRUPTS .................................................................................. 4-8
Comparator Input Match Interrupt................................................................ 4-8
Input Capture Interrupt................................................................................. 4-8
CURRENT DETECT INTERRUPT................................................................... 4-8
SECTION 5
RESETS
5.1
5.2
5.3
5.3.1
5.3.2
5.3.3
5.3.4
5.4
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
POWER-ON RESET ........................................................................................ 5-2
EXTERNAL RESET ......................................................................................... 5-2
INTERNAL RESETS ........................................................................................ 5-2
Power-On Reset (POR) ............................................................................... 5-2
Computer Operating Properly (COP) Reset ................................................ 5-3
Low Voltage Reset (LVR) ............................................................................ 5-4
Illegal Address Reset................................................................................... 5-4
RESET STATES .............................................................................................. 5-4
CPU ............................................................................................................. 5-4
I/O Registers................................................................................................ 5-4
Core Timer................................................................................................... 5-5
COP Watchdog............................................................................................ 5-5
16-Bit Programmable Timer......................................................................... 5-5
SM-Bus Serial Interface............................................................................... 5-5
Analog Subsystem....................................................................................... 5-6
SECTION 6
LOW POWER MODES
6.1
6.2
STOP MODE.................................................................................................... 6-3
WAIT MODE .................................................................................................... 6-4
MC68HC05SB7
REV 2.1
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MOTOROLA
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August 27, 1998
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
Section
6.3
6.4
Page
DATA-RETENTION MODE.............................................................................. 6-4
SLOW MODE................................................................................................... 6-5
SECTION 7
INPUT/OUTPUT PORTS
7.1
7.1.1
7.1.2
7.2
7.3
7.4
PARALLEL PORTS.......................................................................................... 7-1
Port Data Registers ..................................................................................... 7-2
Port Data Direction Registers ...................................................................... 7-2
PORT A............................................................................................................ 7-2
PORT B............................................................................................................ 7-2
PORT C............................................................................................................ 7-2
SECTION 8
SYSTEM CLOCK
8.1
CLOCK SOURCES .......................................................................................... 8-1
8.2
VCO CLOCK SPEED....................................................................................... 8-2
8.2.1
VCO Slow Mode .......................................................................................... 8-2
8.2.2
Setting the VCO Speed ............................................................................... 8-3
SECTION 9
CORE TIMER
9.1
9.2
9.3
9.4
9.5
CORE TIMER STATUS AND CONTROL REGISTER..................................... 9-2
CORE TIMER COUNTER REGISTER (CTCR) ............................................... 9-3
COP WATCHDOG ........................................................................................... 9-4
CORE TIMER DURING WAIT MODE.............................................................. 9-5
CORE TIMER DURING STOP MODE............................................................. 9-5
SECTION 10
16-BIT TIMER
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
TIMER REGISTERS (TMRH, TMRL)............................................................. 10-2
ALTERNATE COUNTER REGISTERS (ACRH, ACRL) ................................ 10-4
INPUT CAPTURE REGISTERS .................................................................... 10-5
OUTPUT COMPARE REGISTERS ............................................................... 10-7
TIMER CONTROL REGISTER (TCR) ........................................................... 10-9
TIMER STATUS REGISTER (TSR)............................................................. 10-10
TIMER OPERATION DURING WAIT MODE............................................... 10-11
TIMER OPERATION DURING STOP MODE .............................................. 10-11
SECTION 11
PULSE WIDTH MODULATOR
11.1
11.2
11.3
11.4
D/A DATA REGISTERS (DAC0-DAC3) ......................................................... 11-2
MUX CHANNEL ENABLE REGISTER (MCER) ............................................ 11-3
PWM DURING WAIT MODE ......................................................................... 11-4
PWM DURING STOP MODE......................................................................... 11-4
MOTOROLA
iii
MC68HC05SB7
REV 2.1
模拟与混合信号
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