1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
1/2-INCH CMOS ACTIVE-
PIXEL CMOS IMAGE
SENSOR
Features
• Array Format: Active: 659H x 494V
• Pixel Size and Type: 9.9µm x 9.9µm TrueSNAP™
(shuttered-node active pixel)
• Optical Format: 1/2-inch
• Frame Rate: 0-200 frames/sec progressive scan
• Data Rate: 66 MB/s (master clock 66 MHz)
• Responsivity: 2.0 V/lux-sec with source Illumination
at 550nm
• SNR: 45dB
• ADC: On-chip, 10-bit
• Power: 130mW at 200 fps
• Supply Voltage: +3.3V
• Internal Intra-Scene Dynamic Range: 60dB
• Operating Temperature: -5°C to +70°C
• Output: 10-bit digital through a single port
• Shutter: TrueSNAP freeze-frame electronic shutter
• Interface Mode: Master/Snapshot/Slave (with
simultaneous or sequential exposure/readout)
• Shutter Efficiency: 98.5%
• Shutter Exposure Time:
• Master Mode or Snapshot Mode: 2 rows to 256
frames (20µs to 1.3 sec with 66 MHz clock)
• Slave Mode: user controlled
• Gain: 1x–18x (step size = 1) or 0.5x–9x
(step size = 0.5)
• Control Interface: Two-wire serial interface
• Package: 48-pin CLCC
• Timing and Control:
On-chip:
• ADC controls, output multiplexing, ADC calibra-
tion via two-wire serial interface, exposure time,
read/write ADC calibration coefficients, window
size and location, gain, biases, master vs. snap-
shot vs. slave, simultaneous vs. continuous expo-
sure/readout, progressive vs. interlace, ADC
reference, vertical and horizontal blanking.
Off-chip:
• Exposure trigger (snapshot mode), exposure and
readout timing (slave mode)
• Color Specifications: monochrome or color (Bayer
pattern)
MT9V403
Micron Part Number: MT9V403C12ST
Description
The Micron
®
Imaging MT9V403 VGA-based CMOS
active-pixel sensor has a 1/2-inch optical format and
delivers superb resolution at a turbocharged 200 fps,
making it the perfect solution for machine vision
assembly lines, airbag deployment, golf swing analysis,
and special effects in movies. The freeze-frame shutter
allows the signal charges of all pixels to be integrated
in parallel—all pixels start integrating simultaneously
and stop integrating simultaneously. The charges are
then sampled into pixel analog memories (one mem-
ory per pixel) and consequently, row by row, are digi-
tized and read out-of-chip. The sensor works in
master, snapshot, or slave mode. In master mode it
generates the readout timing on-chip. In snapshot
mode it accepts an external trigger and then generates
the readout timing. In slave mode the sensor accepts
external readout timing. The integration time is pro-
grammed through the two-wire serial interface (mas-
ter or snapshot mode) or controlled via externally-
generated control signals (slave mode).
The scanning mode can be progressive or inter-
laced. There is also an option to scan just a window of
interest by choosing start row and column and stop
row and column. The user can control the frame rate
and row rate through the use of vertical and horizontal
blanking as well as the master clock frequency.
The readout of the data out of the chip can be done
simultaneously with integration and ADC operation
due to the two-cell SRAM which allows data from the
previously converted row to be shifted into the output
memory for readout.
The sensor’s ADCs contain special self-calibrating
circuitry that allow the sensor to reduce its own col-
umn-wise fixed pattern noise. The calibration coeffi-
cients can be read from, and written to, the sensor.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 1: Block Diagram
Expose
Frame
Row
Sensor
Interface
Block
Control
Logic
Row
Decoder
Pixel Array
System
Clock
Reset
Gain Control
Column PGA
Calibration Data
System
Clock
System
Data
Two-Wire
Serial
Interface
Column ADCs and
calibration memory
667H x 10 SRAM (x2)
ADC and Output Registers
Output (9:0)
Readout Control
Table 1:
Pin Description
TYPE
Input
Input
Input
DESCRIPTIONS
Clock input for entire chip. Maximum design frequency is 66 MHz (50 percent,
±5 percent duty cycle).
Global logic RESET function (asynchronous). Active low pulse with minimum
duration 200ns.
Slave mode input signal. Starts row processing sequence of the pixel row (i.e.,
pixel readout, ADC conversion, and writing of data to ADC registers). The rising
edge of ROW_STRT should be synchronous with the falling edge of SYSCLK. A
one-clock cycle wide active high pulse. The two-wire serial interface register
setting switches this pin between input and output.
Slave mode input signal. An active LOW signal that enables the column counter
and initiates the readout process. Causes the 10-bit output port to be updated
with data on the rising edge of the system clock. The two-wire serial interface
register setting switches this pin between input and output.
Trigger for snapshot mode. The two-wire serial interface register setting
switches this pin between input and output. No connection should be made in
slave mode.
Slave mode input signal. Active low pulse that resets all photodetectors,
starting a new integration cycle. No connection should be made in master
mode or snapshot mode.
Slave mode input signal. Active low pulse that controls transfer of charge from
photodetector to memory inside each pixel for the entire pixel array. No
connection should be made in master mode or snapshot mode.
Slave mode input signal. Active low pulse to reset all pixel memories. No
connection should be made in master mode or snapshot mode.
Serial port clock. Maximum frequency is 1 MHz.
Bias setting voltage for VLN_AMP or VLN_OUT. VLN_AMP and VLN_OUT can be
individually disconnected from their internal biases via the two-wire serial
interface and driven by this input.
Bias setting voltage for pixel source following operating current.
Bias setting voltage for the column source follower operating current.
Dark offset cancellation. Polarity of offset is set via the two-wire serial
interface.
Op amp bias.
PIN
NUMBERS SIGNAL NAME
37
33
30
SYSCLK
LRST_N
ROW_STRT
31
LD_SHFT_N
Input
29
EXPOSE
Input
26
PG_N
Input
25
TX_N
Input
24
38
18
RESMEM
SCLK
VLNS
Input
Input
Input
17
19
13
16
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
VLN1
VLP
VOFF
V
REF
Input
Input
Input
Input
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Table 1:
Pin Description (continued)
TYPE
Input
Input
Input
Input
DESCRIPTIONS
ADC reference voltage that sets the maximum input signal level, setting the
size of the least significant bit (LSB) in the analog to digital conversion process.
ADC bias.
ADC reference used for the calibration operation.
Slave mode input signal. Active low pulse to reset row and column counters,
providing frame synchronization. Low duration should be at least two-clock
cycles wide. An input that is held LOW also sets the sensor in LOW, per standby
mode, until it is released. Signal is pulled up on-chip.
The user should ground this pin.
Offset that may be needed for very short exposure conditions.
Bias setting voltage for the ADC operating current.
Serial port data.
Master mode and snapshot mode output signal. Active HIGH during readout.
The two-wire serial interface register setting switches this pin between input
and output.
Master mode and snapshot mode output signal. Active HIGH when image data
are on data output bus. The two-wire serial interface register setting switches
this pin between input and output.
Master mode output signal. Active HIGH during exposure. The two-wire serial
interface register setting switches this pin between input and output.
Pixel output data bit 9 (MSB).
Pixel output data bit 8.
Pixel output data bit 7.
Pixel output data bit 6.
Pixel output data bit 5.
Pixel output data bit 4.
Pixel output data bit 3.
Pixel output data bit 2.
Pixel output data bit 1.
Pixel output data bit 0 (LSB).
3.3V power supply for analog signal processing circuitry.
Power supply for pixel array. Set for 2.5V.
Ground for analog signal processing circuitry.
3.3V digital power supply.
Ground for digital circuitry.
PIN
NUMBERS SIGNAL NAME
9
8
7
32
V
REF
1
V
REF
1DRV
V
REF
2
FRAME_SYNC_N
14
23
21
39
30
VTEST
VRSTLOW
VLN2
SDATA
FRAME_VALID
Input
Input
Input
Input/
Output
Output
31
ROW_VALID
Output
29
41
40
45
42
46
47
48
1
2
3
12, 22
20
10, 11, 15
6, 27, 36,
43
4, 5, 28, 34,
35, 44
EXPOSE
DATA9
DATA8
DATA7
DATA6
DATA5
DATA4
DATA3
DATA2
DATA1
DATA0
V
AA
VRST_PIX
A
GND
V
DD
D
GND
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Power
Power
Power
Power
Power
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Pixel Data Format
The pixel array descriptions and details are shown
below.
signals utilized in master mode are depicted in
Figure 4. In master mode, the start of the integration
period is determined internal to the MT9V403.
Figure 2: Pixel Array Description
(502, 667)
8
Figure 4: Master Mode Interface
Signals
EXPOSE
SYSCLK
Dark and Isolation
Pixels
Active Pixel Array
FRAME_VALID
494
CONTROLLER
ROW_VALID
DATA
MT9V4O3
(1, 1)
LRST_N
8
659
Figure 3: Pixel Color Pattern Detail
(Bottom Left Corner)
black pixels
G
B
G
B
G
B
G
R
G
R
G
R
G
R
G
B
G
B
G
B
G
R
G
R
G
R
G
R
G
B
G
B
G
B
G
R
G
R
G
R
G
R
G
B
G
B
G
B
G
Output Format and Timing
The sensor can operate in three interface modes:
master, snapshot, or slave mode. Additionally, master
mode can be setup to allow simultaneous integration
and readout (simultaneous master mode) or sequen-
tial integration and readout (sequential master mode).
Mode selection is done via the two-wire serial inter-
face, taking less than one frame time to switch
between modes.
The default register settings program the imager to
read out the visible pixels. Therefore, the start row is 1,
start column is 9, end row is 480 and the end column is
648.
Master Mode
In master mode the sensor internally generates the
timing to initiate exposure and readout. The interface
The integration time is pre-programmed via the
two-wire serial interface and indicated by the EXPOSE
signal going HIGH. When the sensor commences, the
readout process the FRAME_VALID, ROW_VALID, and
DATA signals are output, as shown in Figure 5 on
page 5.
The master mode row synchronization waveform
relationships are as shown in Figure 5 on page 5. The
FRAME_VALID signal goes HIGH, indicating the start
of frame, and 2.5 clock cycles later the ROW_VALID
signal goes HIGH, indicating the start of the first row.
The first data bit is valid on the first falling edge of
SYSCLK after ROW_VALID goes HIGH. The remaining
665 pixels for the row are valid on the subsequent fall-
ing edges of SYSCLK, after which ROW_VALID returns
to the LOW state. (Please note that in master mode 648
pixels are readout for each row.) The ROW_VALID will
then be an active HIGH envelope for subsequent rows
and the FRAME_VALID signal will be an active HIGH
envelope for subsequent frames. The time required for
one complete row operation is 671 clock cycles: 1 clock
cycle delay + 666 columns + 4 clock cycles when
ROW_VALID is LOW. With a SYSCLK of 66 MHz, this
translates into a row time of 10.2µs and a frame time of
5.1ms for full resolution (502 rows). This assumes there
is no vertical blanking or horizontal blanking and that
the exposure time is less than 5.1ms. If exposure time
becomes greater than 5.1ms, the frame time then
becomes the inverse of the exposure time (1/[exposure
time]).
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
1/2-INCH VGA (WITH FREEZE-FRAME) CMOS
ACTIVE-PIXEL DIGITAL IMAGE SENSOR
Figure 5: Master Mode Row Timing Diagram
1
12
652
653
671
671
+
169
1
12
SYSCLK
(input)
ROW _VALID
(output)
DATA [9:0]
(output)
((
))
((
))
((
))
((
))
Horizontal Blanking
((
))
XXX
9
10
((
))
((
))
648
649
XXX
((
))
((
))
9
10
NOTE:
Horizontal blanking is nominally 35 rows, and may be increased using register 5.
In master mode the frame rate is controlled by
inserting vertical and/or horizontal blanking periods
during readout, or by changing the input master clock
(SYSCLK) frequency (i.e., slowing the sensor down), or
by changing the number of rows being readout (i.e.,
window size). Table 2 shows some examples of how the
frame rate changes with window resolution and clock
speed.
Table 2:
Frame Rate vs. Resolution and Clock Speed
CLOCK SPEED (SYSCLK)
66 MHz
66 MHz
66 MHz
66 MHz
24 MHz
24MHz
24 MHz
24 MHz
10 MHz
FRAME RATE (FRAMES/SECOND)
196
392
784
1568
70
140
280
560
30
No blanking, exposure < readout
RESOLUTION (# ROWS)
502 (full resolution)
251
125
63
502 (full resolution)
251
125
63
502 (full resolution)
When horizontal blanking is utilized, the
ROW_VALID stays LOW for an additional user-pro-
grammable number of clock cycles after each row
readout. As a result the row time becomes:
RT = (1 + 66 6+ 4 + HB) x (1/fsysclk)
where HB is the horizontal blanking in SYSCLK
cycles (255 clock maximum) specified in register 5.
When vertical blanking is utilized, the FRAME_
VALID signal stays LOW for an additional user pro-
grammable number of rows after the frame is readout
(if exposure time < readout time) or exposed (if expo-
sure time > readout time). Table 3 on page 6 shows the
various scenarios for calculating the frame time, where
VB is the vertical blanking in rows (255 rows maxi-
mum) specified in register 6. The default vertical
blanking is one SYSCLK cycle, so the true vertical
blanking time is the number of blanking rows pro-
grammed plus one clock cycle.
09005aef80c07280
MT9V403_DS.fm - Rev. B 1/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology. Inc.
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