CAT93C56, CAT93C57
2-Kb Microwire Serial
CMOS EEPROM
CAT93C57 Not Recommended for New
Designs: Replace with CAT93C56
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Description
The CAT93C56/57 is a 2−kb CMOS Serial EEPROM device which
is organized as either 128 registers of 16 bits (ORG pin at V
CC
) or 256
registers of 8 bits (ORG pin at GND). Each register can be written (or
read) serially by using the DI (or DO) pin. The CAT93C56/57 features
sequential read and self−timed internal write with auto−clear. On−chip
Power−On Reset circuitry protects the internal logic against powering
up in the wrong state.
Features
SOIC−8
V or W SUFFIX
CASE 751BD
SOIC−8 EIAJ
X SUFFIX
CASE 751BE
TDFN−8
VP2 SUFFIX
CASE 511AK
•
•
•
•
•
•
•
•
•
•
•
•
High Speed Operation: 2 MHz
1.8 V to 5.5 V Supply Voltage Range
Selectable x8 or x16 Memory Organization
Sequential Read
Software Write Protection
Power−up Inadvertent Write Protection
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Ranges
8−pin PDIP, SOIC, TSSOP and 8−pad TDFN Packages
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
V
CC
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
PIN CONFIGURATIONS
CS
SK
DI
DO
1
2
3
4
8 V
CC
7 NC
6 ORG
5 GND
NC
V
CC
CS
SK
1
2
3
4
8 ORG
7 GND
6 DO
5 DI
PDIP (L), SOIC (V, X),
TSSOP (Y), TDFN (VP2)
SOIC (W*)
* SOIC (W) rotated pin−out package
not recommended for new designs
PIN FUNCTION
Pin Name
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
Power Supply
Ground
Memory Organization
No Connection
ORG
CS
SK
DI
CAT93C56
CAT93C57
DO
CS
SK
DI
DO
V
CC
GND
GND
Figure 1. Functional Symbol
NOTE: When the ORG pin is connected to V
CC
, the x16 organization is selected.
When it is connected to ground, the x8 pin is selected. If the ORG pin is left
unconnected, then an internal pullup device will select the x16 organization.
ORG
NC
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 15 of this data sheet.
©
Semiconductor Components Industries, LLC, 2014
1
May, 2014 − Rev. 19
Publication Order Number:
CAT93C56/D
CAT93C56, CAT93C57
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 1)
Ratings
−65 to +150
−0.5 to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than V
CC
+ 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than V
CC
+ 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Block Mode, V
CC
= 5 V, 25°C
Table 3. D.C. OPERATING CHARACTERISTICS, CAT93C56
(V
CC
= +1.8 V to +5.5 V, T
A
=−40°C to +125°C unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
Parameter
Power Supply
Current (Write)
Power Supply
Current (Read)
Power Supply
Current (Standby)
(x8 Mode)
Power Supply
Current (Standby)
(x16 Mode)
Input Leakage
Current
Output Leakage
Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1 MHz, V
CC
= 5.0 V
f
SK
= 1 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
,
CS = GND ORG = GND
V
IN
= GND or V
CC
, CS =
GND ORG = Float or V
CC
V
IN
= GND to V
CC
T
A
= −40°C to +85°C
T
A
= −40°C to +125°C
T
A
= −40°C to +85°C
T
A
= −40°C to +125°C
T
A
= −40°C to +85°C
T
A
= −40°C to +125°C
V
OUT
= GND to V
CC
,
CS = GND
4.5 V
v
V
CC
< 5.5 V
4.5 V
v
V
CC
< 5.5 V
1.8 V
v
V
CC
< 4.5 V
1.8 V
v
V
CC
< 4.5 V
4.5 V
v
V
CC
< 5.5 V,
I
OL
= 2.1 mA
4.5 V
v
V
CC
< 5.5 V,
I
OH
= −400
mA
1.8 V
v
V
CC
< 4.5 V,
I
OL
= 1 mA
1.8 V
v
V
CC
< 4.5 V,
I
OH
= −100
mA
V
CC
− 0.2
2.4
0.2
T
A
= −40°C to +85°C
T
A
= −40°C to +125°C
−0.1
2
0
V
CC
x 0.7
Min
Max
1
500
2
4
1
2
1
2
1
2
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
V
V
V
V
V
V
V
V
mA
mA
mA
Units
mA
mA
mA
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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CAT93C56, CAT93C57
Table 4. D.C. OPERATING CHARACTERISTICS, CAT93C57, Die Rev. E – Mature Product
(NOT RECOMMENDED FOR NEW DESIGNS)
(V
CC
= +1.8 V to +5.5 V, T
A
=−40°C to +125°C unless otherwise specified.)
Symbol
I
CC1
I
CC2
I
SB1
I
SB2
I
LI
I
LO
V
IL1
V
IH1
V
IL2
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Parameter
Power Supply Current (Write)
Power Supply Current (Read)
Power Supply Current (Standby)
(x8 Mode)
Power Supply Current (Standby)
(x16 Mode)
Input Leakage Current
Output Leakage Current
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
Test Conditions
f
SK
= 1 MHz, V
CC
= 5.0 V
f
SK
= 1 MHz, V
CC
= 5.0 V
V
IN
= GND or V
CC
, CS = GND
ORG = GND
V
IN
= GND or V
CC
, CS = GND
ORG = Float or V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
, CS = GND
4.5 V
v
V
CC
< 5.5 V
4.5 V
v
V
CC
< 5.5 V
1.8 V
v
V
CC
< 4.5 V
1.8 V
v
V
CC
< 4.5 V
4.5 V
v
V
CC
< 5.5 V, I
OL
= 2.1 mA
4.5 V
v
V
CC
< 5.5 V, I
OH
= −400
mA
1.8 V
v
V
CC
< 4.5 V, I
OL
= 1 mA
1.8 V
v
V
CC
< 4.5 V, I
OH
= −100
mA
V
CC
− 0.2
2.4
0.2
−0.1
2
0
V
CC
x 0.7
Min
Max
3
500
10
10
1
1
0.8
V
CC
+ 1
V
CC
x 0.2
V
CC
+ 1
0.4
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
Table 5. PIN CAPACITANCE
(T
A
= 25°C, f = 1 MHz, V
CC
= 5 V)
Symbol
C
OUT
(Note 4)
C
IN
(Note 4)
Test
Output Capacitance (DO)
Input Capacitance (CS, SK, DI, ORG)
Conditions
V
OUT
= 0 V
V
IN
= 0 V
Min
Typ
Max
5
5
Units
pF
pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
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CAT93C56, CAT93C57
Table 6. A.C. CHARACTERISTICS
(Note 5)
, CAT93C56
(V
CC
= +1.8V to +5.5V, T
A
= −40°C to +125°C, unless otherwise specified.)
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 6)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
0.25
0.25
0.25
0.25
2000
Parameter
Min
50
0
100
100
0.25
0.25
100
5
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
Table 7. A.C. CHARACTERISTICS
(Note 5)
, CAT93C57, Die Rev. E – Mature Product
(NOT RECOMMENDED FOR NEW DESIGNS)
Limits
V
CC
= 1.8 V − 5.5 V
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 6)
t
EW
t
CSMIN
t
SKHI
t
SKLOW
t
SV
SK
MAX
Parameter
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High−Z
Program/Erase Pulse Width
Minimum CS Low Time
Minimum SK High Time
Minimum SK Low Time
Output Delay to Status Valid
Maximum Clock Frequency
DC
1
1
1
1
250
DC
Min
200
0
400
400
1
1
400
10
0.5
0.5
0.5
0.5
500
DC
Max
V
CC
= 2.5 V − 5.5 V
Min
100
0
200
200
0.5
0.5
200
10
0.25
0.25
0.25
0.25
1000
Max
V
CC
= 4.5 V − 5.5 V
Min
50
0
100
100
0.25
0.25
100
10
Max
Units
ns
ns
ns
ns
ms
ms
ns
ms
ms
ms
ms
ms
kHz
Table 8. POWER−UP TIMING
(Notes 6 and 7)
Symbol
t
PUR
t
PUW
Power−up to Read Operation
Power−up to Write Operation
Parameter
Max
1
1
Units
ms
ms
5. Test conditions according to “A.C. Test Conditions” table.
6. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate
AEC−Q100 and JEDEC test methods.
7. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
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CAT93C56, CAT93C57
Table 9. A.C. TEST CONDITIONS
Input Rise and Fall Times
Input Pulse Voltages
Timing Reference Voltages
Input Pulse Voltages
Timing Reference Voltages
Output Load
≤
50 ns
0.4 V to 2.4 V
0.8 V, 2.0 V
0.2 V
CC
to 0.7 V
CC
0.5 V
CC
4.5 V
v
V
CC
v
5.5 V
4.5 V
v
V
CC
v
5.5 V
1.8 V
v
V
CC
v
4.5 V
1.8 V
v
V
CC
v
4.5 V
Current Source I
OLmax
/I
OHmax
; CL=100 pF
Device Operation
The CAT93C56/57 is a 2048−bit nonvolatile memory
intended for use with industry standard microprocessors.
The CAT93C56/57 can be organized as either registers of 16
bits or 8 bits. When organized as X16, seven 10−bit
instructions for 93C57 or seven 11−bit instructions for
93C56 control the reading, writing and erase operations of
the device. When organized as X8, seven 11−bit instructions
for 93C57 or seven 12−bit instructions for 93C56 control the
reading, writing and erase operations of the device. The
CAT93C56/57 operates on a single power supply and will
generate on chip, the high voltage required during any write
operation.
Instructions, addresses, and write data are clocked into the
DI pin on the rising edge of the clock (SK). The DO pin is
normally in a high impedance state except when reading data
from the device, or when checking the ready/busy status
after a write operation. The serial communication protocol
follows the timing shown in Figure 2.
The ready/busy status can be determined after the start of
internal write cycle by selecting the device (CS high) and
polling the DO pin; DO low indicates that the write
operation is not completed, while DO high indicates that the
device is ready for the next instruction. If necessary, the DO
pin may be placed back into a high impedance state during
chip select by shifting a dummy “1” into the DI pin. The DO
pin will enter the high impedance state on the rising edge of
the clock (SK). Placing the DO pin into the high impedance
state is recommended in applications where the DI pin and
the DO pin are to be tied together to form a common DI/O
pin.
t
SKHI
SK
t
DIS
DI
t
CSS
CS
VALID
t
SKLOW
t
CSH
t
DIH
VALID
t
DIS
DO
t
PD0
, t
PD1
DATA VALID
t
CSMN
Figure 2. Synchronous Data Timing
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