CAT64LC40
4 kb SPI Serial EEPROM
Description
The CAT64LC40 is a 4 kb Serial EEPROM which is configured as
256 registers by 16 bits. Each register can be written (or read) serially
by using the DI (or DO) pin. The CAT64LC40 is manufactured using
ON Semiconductor’s advanced CMOS EEPROM floating gate
technology. It is designed to endure 1,000,000 program/erase cycles
and has a data retention of 100 years. The device is available in 8−pin
DIP, SOIC and TSSOP packages.
Features
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SPI Bus Compatible
Low Power CMOS Technology
2.5 V to 6.0 V Operation
Self−Timed Write Cycle with Auto−Clear
Hardware Reset Pin
Hardware and Software Write Protection
Commercial, Industrial and Automotive Temperature Ranges
Power−up Inadvertent Write Protection
RDY/BSY Pin for End−of−Write Indication
1,000,000 Program/Erase Cycles
100 Year Data Retention
This Device is Pb−Free, Halogen Free/BFR Free and RoHS
Compliant*
V
CC
GND
Pin Name
MEMORY ARRAY
256 x 16
ADDRESS
DECODER
CS
SK
DI
DO
DATA
REGISTER
DI
OUTPUT
BUFFER
MODE DECODE
LOGIC
V
CC
GND
RESET
RDY/BUSY
PDIP−8
P, L SUFFIX
CASE 646AA
SOIC−8
J, W, S, V SUFFIX
CASE 751BD
TSSOP−8
U, Y SUFFIX
CASE 948AL
PIN FUNCTION
Function
Chip Select
Clock Input
Serial Data Input
Serial Data Output
+2.5 V to +6.0 V Power Supply
Ground
Reset
Ready/BUSY Status
RESET
CS
SK
CLOCK
GENERATOR
DO
RDY/BUSY
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
Figure 1. Block Diagram
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2009
September, 2009
−
Rev. 4
1
Publication Order Number:
CAT64LC40/D
CAT64LC40
PIN CONNECTIONS
CS
SK
DI
DO
1
2
3
4
8
7
6
5
V
CC
RDY/BUSY
RESET
GND
RDY/BUSY
V
CC
CS
SK
1
2
3
4
8
7
6
5
RESET
GND
DO
DI
CS
SK
DI
DO
1
2
3
4
8
7
6
5
V
CC
RDY/BUSY
RESET
GND
PDIP−8 (P, L)
CS
SK
DI
DO
SOIC−8 (J, W)
1
2
3
4
8
7
6
5
V
CC
RDY/BUSY
RESET
GND
TSSOP−8 (U, Y)
SOIC−8 (S, V)
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on any Pin with Respect to Ground (Note 1)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 2)
Ratings
−55
to +125
−65
to +150
−2.0
to +V
CC
+2.0
−2.0
to +7.0
1.0
300
100
Unit
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
2. Output shorted for no more than one second. No more than one output shorted at a time.
Table 2. RELIABILITY CHARACTERISTICS
Symbol
N
END
(Note 3)
T
DR
(Note 3)
V
ZAP
(Note 3)
I
LTH
(Notes 3 and 4)
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Parameter
Min
1,000,000
100
2000
100
Max
Units
Cycles/Byte
Years
V
mA
3. This parameter is tested initially and after a design or process change that affects the parameter.
4. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+1 V.
Table 3. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 6.0 V)
Symbol
C
I/O
(Note 5)
C
IN
(Note 5)
Test
Input/Output Capacitance (DO, RDY/BSY)
Input Capacitance (CS, SK, DI, RESET)
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Max
8
6
Units
pF
pF
5. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT64LC40
Table 4. D.C. OPERATING CHARACTERISTICS
(V
CC
= +2.5 V to +6.0 V, unless otherwise specified.)
Limits
Symbol
I
CC
I
CCP
I
SB
(Note 6)
I
LI
I
LO
V
IL
V
IH
V
IL
V
IH
V
OH
(Note 6)
Parameter
Operating Current
EWEN, EWDS, READ
Program Current
2.5 V
6.0 V
2.5 V
6.0 V
Standby Current
Input Leakage Current
Output Leakage Current
Low Level Input Voltage, DI
High Level Input Voltage, DI
Low Level Input Voltage,
CS,
SK, RESET
High Level Input Voltage,
CS,
SK, RESET
High Level Output Voltage
2.5 V
6.0 V
I
OH
=
−10
mA
I
OH
=
−10
mA
I
OH
=
−400
mA
V
OL
(Note 6)
Low Level Output Voltage
2.5 V
6.0 V
6. V
OH
and V
OL
spec applies to READY/BUSY pin also.
I
OL
= 10
mA
I
OL
= 2.1 mA
V
IN
= GND or V
CC
CS
= V
CC
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
−0.1
V
CC
x 0.7
−0.1
V
CC
x 0.8
V
CC
−
0.3
V
CC
−
0.3
2.4
0.4
0.4
Test Conditions
f
SK
= 250 kHz
f
SK
= 1 MHz
Min
Typ
Max
0.4
1
2
3
3
2
10
V
CC
x 0.3
V
CC
+ 0.5
V
CC
x 0.2
V
CC
+ 0.5
Units
mA
mA
mA
mA
mA
mA
mA
V
V
V
V
V
V
V
V
V
Table 5. A.C. OPERATING CHARACTERISTICS
(V
CC
= +2.5 V to +6.0 V, unless otherwise specified.)
Limits
Symbol
t
CSS
t
CSH
t
DIS
t
DIH
t
PD1
t
PD0
t
HZ
(Note 7)
t
CSMIN
t
SKHI
t
SKLOW
t
SV
f
SK
t
RESS
t
RESMIN
t
RESH
t
RC
CS Setup Time
CS Hold Time
DI Setup Time
DI Hold Time
Output Delay to 1
Output Delay to 0
Output Delay to High Impedance
Minimum
CS
High Time
Minimum SK High Time
2.5 V
4.5 V
−
6.0 V
Minimum SK Low Time
2.5 V
4.5 V
−
6.0 V
Output Delay to Status Valid
Maximum Clock Frequency
2.5 V
4.5 V
−
6.0 V
Reset to
CS
Setup Time
Minimum RESET High Time
RESET to READY Hold Time
Write Recovery
250
1000
0
250
0
100
ns
ns
ns
ns
250
1000
400
1000
400
500
ns
kHz
ns
Parameter
Min
100
100
200
200
300
300
500
Typ
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
7. This parameter is sampled but not 100% tested.
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CAT64LC40
Table 6. POWER−UP TIMING
(Notes 8 and 9)
Symbol
t
PUR
t
PUW
Power−Up to Read Operation
Power−Up to Program Operation
Parameter
Min
Max
10
1
Units
ms
ms
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. t
PUR
and t
PUW
are the delays required from the time V
CC
is stable until the specified operation can be initiated.
Table 7. WRITE CYCLE LIMITS
Symbol
t
WR
Program Cycle Time
Parameter
2.5 V
4.5 V
−
6.0 V
Min
Max
10
5
Units
ms
Table 8. INSTRUCTION SET
Instruction
Read
Write
Write Enable
Write Disable
[Write All Locations] (Note 10)
Opcode
10101000
10100100
10100011
10100000
10100001
Address
A7 A6 A5 A4 A3 A2 A1 A0
A7 A6 A5 A4 A3 A2 A1 A0
XXXXXXXX
XXXXXXXX
XXXXXXXX
D15
−
D0
Data
D15
−
D0
D15
−
D0
10. (Write All Locations) is a test mode operation and is therefore not included in the AC/DC Operations specifications.
V
CC
x 0.8
INPUT PULSE LEVELS
V
CC
x 0.2
V
CC
x 0.7
V
CC
x 0.3
REFERENCE POINTS
Figure 2. AC Testing Input/Output Waveform
(Notes 11, 12 and 13) (C
L
= 100 pF)
11. Input Rise and Fall Times (10% to 90%) < 10 ns.
12. Input Pulse Levels = V
CC
x 0.2 and V
CC
x 0.8.
13. Input and Output Timing Reference = V
CC
x 0.3 and V
CC
x 0.7.
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CAT64LC40
Device Operation
The CAT64LC40 is a 4 kb nonvolatile memory intended
for use with all standard controllers. The CAT64LC40 is
organized in a 256 x 16 format. All instructions are based on
an 8−bit format. There are four 16−bit instructions: READ,
WRITE, EWEN, and EWDS. The CAT64LC40 operates on
a single power supply ranging from 2.5 V to 6.0 V and it has
an on−chip voltage generator to provide the high voltage
needed during a programming operation. Instructions,
addresses and data to be written are clocked into the DI pin
RESET
t
RESS
SK
t
DIS
DI
t
CSS
CS
t
PD0
, t
PD1
DO
t
RC
RDY/BUSY
t
RESH
t
SV
t
HZ
t
SV
t
CSH
t
CSMIN
t
DIH
t
SKLOW
t
SKHI
on the rising edge of the SK clock. The DO pin is normally
in a high impedance state except when outputting data in a
READ operation or outputting RDY/BSY status when
polled during a WRITE operation.
The format for all instructions sent to this device includes
a 4−bit start sequence, 1010, a 4−bit op code and an 8−bit
address field or dummy bits. For a WRITE operation, a
16−bit data field is also required following the 8−bit address
field.
Figure 3. Synchronous Data Timing
RESET
SK
CS
DI
1
0
1
0
1
0
0
0
ADDRESS*
DO
HIGH
D15 D14
D1 D0
RDY/BUSY
Figure 4. Read Instruction Timing
*Please check the instruction set table for address
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