CAT28C17A
16 kb CMOS Parallel
EEPROM
Description
The CAT28C17A is a fast, low power, 5 V−only CMOS Parallel
EEPROM organized as 2K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches, self−timed
write cycle with auto−clear and V
CC
power up/down write protection
eliminate additional timing and protection hardware. DATA Polling and
a RDY/BSY pin signal the start and end of the self−timed write cycle.
Additionally, the CAT28C17A features hardware write protection.
The CAT28C17A is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
10,000 program/erase cycles and has a data retention of 10 years. The
device is available in JEDEC approved 28−pin DIP and SOIC or
32−pin PLCC packages.
Features
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SOIC−28
J, K, W, X SUFFIX
CASE 751BM
•
Fast Read Access Times: 200 ns
•
Low Power CMOS Dissipation:
•
•
•
•
•
•
•
•
– Active: 25 mA Max.
– Standby: 100
mA
Max.
Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
Fast Write Cycle Time: 10 ms Max
End of Write Detection:
−
DATA Polling
−
RDY/BSY Pin
Hardware Write Protection
CMOS and TTL Compatible I/O
10,000 Program/Erase Cycles
10 Year Data Retention
Commercial, Industrial and Automotive Temperature Ranges
PDIP−28
P, L SUFFIX
CASE 646AE
PLCC−32
N, G SUFFIX
CASE 776AK
PIN FUNCTION
Pin Name
A
0
−A
10
I/O
0
−I/O
7
RDY/BUSY
CE
OE
WE
V
CC
V
SS
NC
Function
Address Inputs
Data Inputs/Outputs
Ready/BUSY Status
Chip Enable
Output Enable
Write Enable
5 V Supply
Ground
No Connect
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 12 of this data sheet.
©
Semiconductor Components Industries, LLC, 2009
December, 2009
−
Rev. 4
1
Publication Order Number:
CAT28C17A/D
CAT28C17A
PIN CONFIGURATION
A
7
NC
RDY/BUSY
NC
V
CC
WE
NC
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
TOP VIEW
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
DIP Package (P, L)
SOIC Package (J, K, W, X)
RDY/BUSY
NC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
V
CC
WE
NC
A
8
A
9
NC
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
PLCC Package (N, G)
A
8
A
9
NC
NC
OE
A
10
CE
I/O
7
I/O
6
A
4
−A
10
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
2,048 x 8
EEPROM
ARRAY
V
CC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
DATA POLLING
& RDY/BUSY
I/O BUFFERS
TIMER
ADDR. BUFFER
& LATCHES
I/O
0
−I/O
7
A
0
−A
3
RDY/BUSY
COLUMN
DECODER
Figure 1. Block Diagram
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2
CAT28C17A
Table 1. MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High−Z
High−Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Table 2. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 1)
C
IN
(Note 1)
Test
Input/Output Capacitance
Input Capacitance
Max
10
6
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Units
pF
pF
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 3)
Ratings
–55 to +125
–65 to +150
–2.0 V to +V
CC
+ 2.0 V
−2.0
to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
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3
CAT28C17A
Table 4. RELIABILITY CHARACTERISTICS
(Note 4)
Symbol
N
END
T
DR
V
ZAP
I
LTH
(Note 5)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Test Method
MIL−STD−883, Test Method 1033
MIL−STD−883, Test Method 1008
MIL−STD−883, Test Method 3015
JEDEC Standard 17
Min
10,000
10
2,000
100
Max
Units
Cycles/Byte
Years
V
mA
4. This parameter is tested initially and after a design or process change that affects the parameter.
5. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+ 1 V.
Table 5. D.C. OPERATING CHARACTERISTICS
(V
CC
= 5 V
±10%,
unless otherwise specified.)
Limits
Symbol
I
CC
I
CCC
(Note 6)
I
SB
I
SBC
(Note 7)
I
LI
I
LO
V
IH
(Note 7)
V
IL
(Note 6)
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Operating, CMOS)
V
CC
Current (Standby, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
I
OH
=
−400
mA
I
OL
= 2.1 mA
3.0
Test Conditions
CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
CE = OE = V
ILC
,
f = 1/t
RC
min, All I/O’s Open
CE = V
IH
, All I/O’s Open
CE = V
IHC
, All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE = V
IH
−10
−10
2
−0.3
2.4
0.4
Min
Typ
Max
35
25
1
100
10
10
V
CC
+ 0.3
0.8
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
6. V
ILC
=
−0.3
V to +0.3 V
7. V
IHC
= V
CC
−0.3
V to V
CC
+ 0.3 V
Table 6. A.C. CHARACTERISTICS, READ CYCLE
(V
CC
= 5 V
±10%,
unless otherwise specified.)
28C17A−20
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ
(Note 8)
t
OLZ
(Note 8)
t
HZ
(Notes 8, 9)
t
OHZ
(Notes 8, 9)
t
OH
(Note 8)
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High−Z Output
OE High to High−Z Output
Output Hold from Address Change
0
0
0
55
55
Parameter
Min
200
200
200
80
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
8. This parameter is tested initially and after a design or process change that affects the parameter.
9. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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CAT28C17A
2.4 V
INPUT PULSE LEVELS
0.45 V
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform
(Note 10)
10. Input rise and fall times (10% and 90%) < 10 ns.
1.3 V
1N914
3.3 K
DEVICE
UNDER
TEST
OUT
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE
(V
CC
= 5 V
±10%,
unless otherwise specified.)
28C17A−20
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
(Note 11)
t
OES
t
OEH
t
WP
(Note 11)
t
DS
t
DH
t
DL
t
INIT
(Note 12)
t
DB
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Data Latch Time
Write Inhibit Period After Power−up
Time to Device Busy
10
100
0
0
150
15
15
150
50
10
50
5
20
80
Parameter
Min
Max
10
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ns
11. A write pulse of less than 20 ns duration will not initiate a write cycle.
12. This parameter is tested initially and after a design or process change that affects the parameter.
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