CAT28C16A
16 kb CMOS Parallel
EEPROM
Description
The CAT28C16A is a fast, low power, 5V−only CMOS Parallel
EEPROM organized as 2K x 8−bits. It requires a simple interface for
in−system programming. On−chip address and data latches,
self−timed write cycle with auto−clear and V
CC
power up/down write
protection eliminate additional timing and protection hardware. DATA
Polling signals the start and end of the self−timed write cycle.
Additionally, the CAT28C16A features hardware write protection.
The CAT28C16A is manufactured using ON Semiconductor’s
advanced CMOS floating gate technology. It is designed to endure
100,000 program/erase cycles and has a data retention of 100 years.
The device is available in JEDEC approved 24−pin DIP and SOIC or
32−pin PLCC packages.
Features
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SOIC−24
J, K, W, X SUFFIX
CASE 751BK
•
Fast Read Access Times: 90 ns, 120 ns, 200 ns
•
Low Power CMOS Dissipation:
•
•
•
•
•
•
•
•
– Active: 25 mA Max.
– Standby: 100
mA
Max.
Simple Write Operation:
– On−chip Address and Data Latches
– Self−timed Write Cycle with Auto−clear
Fast Write Cycle Time: 10 ms Max
End of Write Detection: DATA Polling
Hardware Write Protection
CMOS and TTL Compatible I/O
100,000 Program/Erase Cycles
100 Year Data Retention
Commercial, Industrial and Automotive Temperature Ranges
PIN CONFIGURATION
A
7
NC
NC
NC
V
CC
WE
NC
PDIP−24
L SUFFIX
CASE 646AD
PLCC−32
N, G SUFFIX
CASE 776AK
PIN FUNCTION
Pin Name
A
0
−A
10
I/O
0
−I/O
7
CE
OE
WE
V
CC
V
SS
NC
Function
Address Inputs
Data Inputs/Outputs
Chip Enable
Output Enable
Write Enable
5 V Supply
Ground
No Connect
DIP Package (L)
SOIC Package (J, K, W, X)
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
A
8
A
9
WE
OE
A
10
CE
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
6
A
5
A
4
A
3
A
2
A
1
A
0
NC
I/O
0
PLCC Package (N, G)
ORDERING INFORMATION
A
8
A
9
NC
NC
OE
A
10
CE
I/O
7
I/O
6
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
4 3 2 1 32 31 30
5
29
6
28
7
27
8
26
9
25
TOP VIEW
10
24
11
23
12
22
13
21
14 15 16 17 18 19 20
I/O
1
I/O
2
V
SS
NC
I/O
3
I/O
4
I/O
5
©
Semiconductor Components Industries, LLC, 2009
October, 2009
−
Rev. 6
1
Publication Order Number:
CAT28C16A/D
CAT28C16A
A
4
−A
10
ADDR. BUFFER
& LATCHES
INADVERTENT
WRITE
PROTECTION
ROW
DECODER
2,048 x 8
EEPROM
ARRAY
V
CC
HIGH VOLTAGE
GENERATOR
CE
OE
WE
CONTROL
LOGIC
I/O BUFFERS
DATA POLLING
I/O
0
−I/O
7
TIMER
ADDR. BUFFER
& LATCHES
A
0
−A
3
COLUMN
DECODER
Figure 1. Block Diagram
Table 1. MODE SELECTION
Mode
Read
Byte Write (WE Controlled)
Byte Write (CE Controlled)
Standby, and Write Inhibit
Read and Write Inhibit
H
X
CE
L
L
L
X
H
WE
H
OE
L
H
H
X
H
I/O
D
OUT
D
IN
D
IN
High−Z
High−Z
Power
ACTIVE
ACTIVE
ACTIVE
STANDBY
ACTIVE
Table 2. CAPACITANCE
(T
A
= 25°C, f = 1.0 MHz, V
CC
= 5 V)
Symbol
C
I/O
(Note 1)
C
IN
(Note 1)
Test
Input/Output Capacitance
Input Capacitance
Max
10
6
Conditions
V
I/O
= 0 V
V
IN
= 0 V
Units
pF
pF
1. This parameter is tested initially and after a design or process change that affects the parameter.
Table 3. ABSOLUTE MAXIMUM RATINGS
Parameters
Temperature Under Bias
Storage Temperature
Voltage on Any Pin with Respect to Ground (Note 2)
V
CC
with Respect to Ground
Package Power Dissipation Capability (T
A
= 25°C)
Lead Soldering Temperature (10 secs)
Output Short Circuit Current (Note 3)
Ratings
–55 to +125
–65 to +150
–2.0 V to +V
CC
+ 2.0 V
−2.0
to +7.0
1.0
300
100
Units
°C
°C
V
V
W
°C
mA
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. The minimum DC input voltage is
−0.5
V. During transitions, inputs may undershoot to
−2.0
V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+ 0.5 V, which may overshoot to V
CC
+ 2.0 V for periods of less than 20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
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CAT28C16A
Table 4. RELIABILITY CHARACTERISTICS
(Note 4)
Symbol
N
END
(Note 5)
T
DR
(Notes 5)
V
ZAP
I
LTH
(Note 6)
Endurance
Data Retention
ESD Susceptibility
Latch−Up
Parameter
Min
100,000
100
2,000
100
Max
Units
Cycles/Byte
Years
V
mA
4. This parameter is tested initially and after a design or process change that affects the parameter.
5. For the CAT28C16A−20, the minimum endurance is 10,000 cycles and the minimum data retention is 10 years.
6. Latch−up protection is provided for stresses up to 100 mA on address and data pins from
−1
V to V
CC
+ 1 V.
Table 5. D.C. OPERATING CHARACTERISTICS
(V
CC
= 5 V
±10%,
unless otherwise specified.)
Limits
Symbol
I
CC
I
CCC
(Note 7)
I
SB
I
SBC
(Note 8)
I
LI
I
LO
V
IH
(Note 8)
V
IL
(Note 7)
V
OH
V
OL
V
WI
Parameter
V
CC
Current (Operating, TTL)
V
CC
Current (Operating, CMOS)
V
CC
Current (Standby, TTL)
V
CC
Current (Standby, CMOS)
Input Leakage Current
Output Leakage Current
High Level Input Voltage
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Write Inhibit Voltage
I
OH
=
−400
mA
I
OL
= 2.1 mA
3.0
Test Conditions
CE = OE = V
IL
,
f = 1/t
RC
min, All I/O’s Open
CE = OE = V
ILC
,
f = 1/t
RC
min, All I/O’s Open
CE = V
IH
, All I/O’s Open
CE = V
IHC
, All I/O’s Open
V
IN
= GND to V
CC
V
OUT
= GND to V
CC
,
CE = V
IH
−10
−10
2
−0.3
2.4
0.4
Min
Typ
Max
35
25
1
100
10
10
V
CC
+ 0.3
0.8
Units
mA
mA
mA
mA
mA
mA
V
V
V
V
V
7. V
ILC
=
−0.3
V to +0.3 V
8. V
IHC
= V
CC
−
0.3 V to V
CC
+ 0.3 V
Table 6. A.C. CHARACTERISTICS, READ CYCLE
(V
CC
= 5 V
±10%,
unless otherwise specified.)
28C16A−90
Symbol
t
RC
t
CE
t
AA
t
OE
t
LZ
(Note 9)
t
OLZ
(Note 9)
t
HZ
(Notes 9, 10)
t
OHZ
(Notes 9,
10)
t
OH
(Note 9)
Parameter
Read Cycle Time
CE Access Time
Address Access Time
OE Access Time
CE Low to Active Output
OE Low to Active Output
CE High to High−Z Output
OE High to High−Z Output
Output Hold from Address Change
0
0
0
50
50
0
Min
90
90
90
50
0
0
50
50
0
Max
28C16A−12
Min
120
120
120
60
0
0
55
55
Max
28C16A−20
Min
200
200
200
80
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
9. This parameter is tested initially and after a design or process change that affects the parameter.
10. Output floating (High−Z) is defined as the state when the external data line is no longer driven by the output buffer.
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CAT28C16A
2.4 V
INPUT PULSE LEVELS
0.45 V
2.0 V
0.8 V
REFERENCE POINTS
Figure 2. A.C. Testing Input/Output Waveform
(Note 11)
11. Input rise and fall times (10% and 90%) < 10 ns.
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
C
L
= 100 pF
C
L
INCLUDES JIG CAPACITANCE
Figure 3. A.C. Testing Load Circuit (example)
Table 7. A.C. CHARACTERISTICS, WRITE CYCLE
(V
CC
= 5 V
±10%,
unless otherwise specified.)
28C16A−90
Symbol
t
WC
t
AS
t
AH
t
CS
t
CH
t
CW
(Note 12)
t
OES
t
OEH
t
WP
(Note 12)
t
DS
t
DH
t
DL
t
INIT
(Note 13)
Parameter
Write Cycle Time
Address Setup Time
Address Hold Time
CE Setup Time
CE Hold Time
CE Pulse Time
OE Setup Time
OE Hold Time
WE Pulse Width
Data Setup Time
Data Hold Time
Data Latch Time
Write Inhibit Period After Power−up
0
100
0
0
110
0
0
110
60
0
5
0.05
10
100
Min
Max
5
0
100
0
0
110
0
0
110
60
0
5
0.05
10
100
28C16A−12
Min
Max
5
10
100
0
0
150
15
15
150
50
10
50
5
20
28C16A−20
Min
Max
10
Units
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
12. A write pulse of less than 20 ns duration will not initiate a write cycle.
13. This parameter is tested initially and after a design or process change that affects the parameter.
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CAT28C16A
DEVICE OPERATION
Read
Data stored in the CAT28C16A is transferred to the data bus when WE is held high, and both OE and CE are held low. The
data bus is set to a high impedance state when either CE or OE goes high. This 2−line control architecture can be used to
eliminate bus contention in a system environment.
t
RC
ADDRESS
t
CE
CE
OE
t
OE
WE
V
IH
t
LZ
t
OLZ
t
AA
t
OH
DATA VALID
t
OHZ
t
HZ
DATA VALID
DATA OUT
HIGH−Z
Figure 4. Read Cycle
t
WC
ADDRESS
t
AS
t
CS
CE
t
AH
t
CH
OE
t
OES
WE
t
DL
DATA OUT
HIGH−Z
t
WP
t
OEH
DATA IN
DATA VALID
t
DS
t
DH
Figure 5. Byte Write Cycle [WE Controlled]
Byte Write
A write cycle is executed when both CE and WE are low,
and OE is high. Write cycles can be initiated using either WE
or CE, with the address input being latched on the falling
edge of WE or CE, whichever occurs last. Data, conversely,
is latched on the rising edge of WE or CE, whichever occurs
first. Once initiated, a byte write cycle automatically erases
the addressed byte and the new data is written within 10 ms.
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