Freescale Semiconductor, Inc.
HC05P9AGRS/D
REV 2.0
68HC05P9A
SPECIFICATION
Freescale Semiconductor, Inc...
(General Release)
AR
C
HIV
ED
BY
F
For More Information On This Product,
Go to: www.freescale.com
RE
ES
CA
LE
CSIC MCU Design Group
Oak Hill, Texas
SE
MIC
©
December 18, 1995
ON
DU
CT
OR
, IN
C.
2
006
Freescale Semiconductor, Inc.
Freescale Semiconductor, Inc...
AR
C
HIV
ED
BY
F
For More Information On This Product,
Go to: www.freescale.com
RE
ES
CA
LE
SE
MIC
ON
DU
CT
OR
, IN
C.
2
006
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
SECTION 1
GENERAL DESCRIPTION
1.1
1.2
1.3
1.4
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.6
Freescale Semiconductor, Inc...
Rev. 2.0
For More Information On This Product,
Go to: www.freescale.com
AR
C
HIV
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.4
3.5
Accumulator (A) .............................................................................................. 3-1
Index Register (X) ........................................................................................... 3-1
Condition Code Register (CCR) ...................................................................... 3-1
H — Half Carry ........................................................................................... 3-1
I — Interrupt ................................................................................................ 3-2
N — Negative ............................................................................................. 3-2
Z — Zero ..................................................................................................... 3-2
C — Carry/Borrow ...................................................................................... 3-2
Stack Pointer (SP) ........................................................................................... 3-2
Program Counter (PC) .................................................................................... 3-3
ED
BY
F
RE
SECTION 3
CENTRAL PROCESSING UNIT
ES
CA
2.1
2.2
2.3
ROM ................................................................................................................ 2-3
ROM Security Feature .................................................................................... 2-3
RAM ................................................................................................................ 2-3
LE
SE
SECTION 2
MEMORY
MIC
Features .......................................................................................................... 1-1
Mask Options .................................................................................................. 1-2
MCU Structure ................................................................................................ 1-3
Pin Assignments ............................................................................................. 1-4
Signal Description ........................................................................................... 1-4
V
DD
and V
SS
............................................................................................... 1-4
IRQ ............................................................................................................. 1-4
OSC1 and OSC2 ........................................................................................ 1-5
RESET ........................................................................................................ 1-5
TCMP .......................................................................................................... 1-5
PA0 through PA7 ........................................................................................ 1-5
SDO/PB5, SDI/PB6, and SCK/PB7 ............................................................ 1-6
PC0 through PC7 ........................................................................................ 1-6
PD5 and TCAP/PD7 ................................................................................... 1-6
Input/Output Programming .............................................................................. 1-6
ON
DU
CT
OR
, IN
C.
2
006
Section
Title
Page
iii
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
SECTION 4
INTERRUPTS
4.1
4.2
4.3
4.4
4.5
Hardware Controlled Interrupt Sequence ........................................................ 4-2
Timer Interrupt ................................................................................................. 4-3
External Interrupt ............................................................................................. 4-4
Optional External Interrupts (PA0-PA7) ........................................................... 4-6
Software Interrupt (SWI) ................................................................................. 4-6
SECTION 5
RESETS
Freescale Semiconductor, Inc...
5.1
5.2
5.3
Power-On Reset (POR) .................................................................................. 5-1
RESET Pin ...................................................................................................... 5-1
Computer Operating Properly (COP) Reset .................................................... 5-1
SECTION 6
LOW POWER MODES
ED
7.1
Signal Format .................................................................................................. 7-1
7.1.1
Serial Clock (SCK) ...................................................................................... 7-1
7.1.2
Serial Data Out (SDO) ................................................................................ 7-2
7.1.3
Serial Data In (SDI) ..................................................................................... 7-2
7.2
SIOP Registers ............................................................................................... 7-3
7.2.1
SIOP Control Register (SCR) ..................................................................... 7-3
7.2.2
SIOP Status Register (SSR) ....................................................................... 7-4
7.2.3
SIOP Data Register (SDR) ......................................................................... 7-5
BY
F
RE
ES
SECTION 7
SIMPLE SERIAL INPUT/OUTPUT PORT
CA
8.1
8.2
8.3
8.4
8.5
Counter ........................................................................................................... 8-2
Output Compare Register ............................................................................... 8-3
Input Capture Register .................................................................................... 8-4
Timer Control Register (TCR) $12 .................................................................. 8-5
Timer Status Register (TSR) $13 .................................................................... 8-6
AR
C
HIV
LE
6.1
6.2
6.3
6.2
STOP Instruction.............................................................................................. 6-1
Stop Mode ....................................................................................................... 6-1
Halt Mode......................................................................................................... 6-2
WAIT Instruction............................................................................................... 6-2
SE
SECTION 8
TIMER
MIC
ON
DU
CT
OR
, IN
C.
2
006
Section
Title
Page
iv
For More Information On This Product,
Go to: www.freescale.com
MC68HC05P9A
Rev. 2.0
Freescale Semiconductor, Inc.
GENERAL RELEASE SPECIFICATION
TABLE OF CONTENTS
8.6
8.7
Timer During Wait Mode ................................................................................. 8-7
Timer During Stop Mode ................................................................................. 8-7
SECTION 9
COMPUTER OPERATING PROPERLY (COP)
9.1
9.2
9.3
Resetting The COP ......................................................................................... 9-1
COP During Wait Mode ................................................................................... 9-1
COP During Stop Mode .................................................................................. 9-1
SECTION 10
ANALOG-TO-DIGITAL (A/D) CONVERTER
Freescale Semiconductor, Inc...
Rev. 2.0
For More Information On This Product,
Go to: www.freescale.com
AR
C
12.1 Addressing Modes ........................................................................................ 12-1
12.1.1 Inherent ..................................................................................................... 12-1
12.1.2 Immediate ................................................................................................. 12-2
12.1.3 Direct ........................................................................................................ 12-2
12.1.4 Extended ................................................................................................... 12-2
12.1.5 Indexed, No Offset .................................................................................... 12-2
12.1.6 Indexed, 8-Bit Offset ................................................................................. 12-2
12.1.7 Indexed, 16-Bit Offset ............................................................................... 12-3
12.1.8 Relative ..................................................................................................... 12-3
12.2 Instruction Types ........................................................................................... 12-4
12.2.1 Register/Memory Instructions ................................................................... 12-4
12.2.3 Read-Modify-Write Instructions ................................................................ 12-5
12.2.4 Jump/Branch Instructions ......................................................................... 12-5
12.2.5 Bit Manipulation Instructions ..................................................................... 12-7
12.2.6 Control Instructions ................................................................................... 12-7
12.3 Instruction Set Summary ............................................................................... 12-8
HIV
ED
BY
F
RE
ES
CA
SECTION 12
INSTRUCTION SET
LE
SECTION 11
SELF-CHECK MODE
SE
MIC
10.1
10.2
10.3
10.4
10.5
Conversion Process ....................................................................................... 10-1
A/D Status and Control Register (ADSCR) .................................................... 10-2
A/D Data Register (ADDR)............................................................................. 10-3
A/D Converter During Wait Mode................................................................... 10-4
A/D Converter During Stop or Halt Mode....................................................... 10-4
ON
DU
CT
OR
, IN
C.
2
006
Section
Title
Page
v