Main Menu
CAT28F102
1 Megabit CMOS Flash Memory
FEATURES
s
Fast Read Access Time: 100/120 ns
s
Low Power CMOS Dissipation:
Licensed Intel
second source
s
64K x 16 Word Organization
s
Stop Timer for Program/Erase
s
On-Chip Address and Data Latches
s
JEDEC Standard Pinouts:
–Active: 30 mA max (CMOS/TTL levels)
–Standby: 1 mA max (TTL levels)
–Standby: 100
µ
A max (CMOS levels)
s
High Speed Programming:
–10
µ
s per byte
–1 Sec Typ Chip Program
–40-pin DIP
–44-pin PLCC
–40-pin TSOP
s
100,000 Program/Erase Cycles
s
10 Year Data Retention
s
Electronic Signature
s
0.5 Seconds Typical Chip-Erase
s
12.0V
±
5% Programming and Erase Voltage
s
Commercial,Industrial and Automotive
Temperature Ranges
DESCRIPTION
The CAT28F102 is a high speed 64K x 16-bit electrically
erasable and reprogrammable Flash memory ideally
suited for applications requiring in-system or after-sale
code updates. Electrical erasure of the full memory
contents is achieved typically within 0.5 second.
It is pin and Read timing compatible with standard
EPROM and E
2
PROM devices. Programming and Erase
are performed through an operation and verify algorithm.
The instructions are input via the I/O bus, using a two
write cycle scheme. Address and Data are latched to
free the I/O bus and address bus during the write
operation.
The CAT28F102 is manufactured using Catalyst’s
advanced CMOS floating gate technology. It is designed
to endure 100,000 program/erase cycles and has a data
retention of 10 years. The device is available in JEDEC
approved 40-pin DIP, 44-pin PLCC, or 40-pin TSOP
packages.
I/O0–I/O15
BLOCK DIAGRAM
I/O BUFFERS
ERASE VOLTAGE
SWITCH
WE
COMMAND
REGISTER
PROGRAM VOLTAGE
SWITCH
CE, OE LOGIC
DATA
LATCH
SENSE
AMP
CE
OE
ADDRESS LATCH
Y-GATING
Y-DECODER
1,048,576-BIT
MEMORY
ARRAY
A0–A15
X-DECODER
VOLTAGE VERIFY
SWITCH
© 2001 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
1
Doc. No. 1014, Rev. A
CAT28F102
Main Menu
PIN CONFIGURATION
PIN FUNCTIONS
Pin Name
A
0
–A
15
I/O
0
–I/O
15
CE
OE
WE
39
38
37
36
35
34
33
32
31
A13
A12
A11
A10
A9
VSS
NC
A8
A7
A6
A5
Type
Input
I/O
Input
Input
Input
Function
Address Inputs for
memory addressing
Data Input/Output
Chip Enable
Output Enable
Write Enable
Voltage Supply
Ground
Program/Erase
Voltage Supply
No Connect
PLCC Package (N)
I/O13
I/O14
I/O15
CE
VPP
NC
VCC
NC
A15
A14
WE
I/O12
I/O11
I/O10
I/O9
I/O8
VSS
NC
I/O7
I/O6
I/O5
I/O4
7
8
9
10
11
12
13
14
15
6 5 4 3 2 1 44 43 42 41 40
V
CC
V
SS
V
PP
NC
30
16
29
17
18 19 20 21 22 23 24 25 26 27 28
NC
A0
A1
A2
A3
I/O1
I/O0
OE
I/O3
I/O2
A4
TSOP Package (T14)
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
VSS
28F101-2
DIP Package (P)
VPP
CE
I/O15
I/O14
I/O13
I/O12
I/O11
I/O10
I/O9
I/O8
VSS
I/O7
I/O6
I/O5
I/O4
I/O3
I/O2
I/O1
I/O0
OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
WE
NC
A15
A14
A13
A12
A11
A10
A9
VSS
A8
A7
A6
A5
A4
A3
A2
A1
A0
Reverse TSOP Package (T14R)
A0
A1
A2
A3
A4
A5
A6
A7
A8
GND
A9
A10
A11
A12
A13
A14
A15
NC
WE
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
OE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
GND
I/O8
I/O9
I/O10
I/O11
I/O12
I/O13
I/O14
I/O15
VPP
CE
Doc. No. 1014, Rev. A
2
Main Menu
CAT28F102
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias ................. –55°C to +105°C
Storage Temperature ....................... –65°C to +150°C
Voltage on Any Pin with
Respect to Ground
(1)
........... –0.6V to +V
CC
+ 2.0V
Voltage on Pin A
9
with
Respect to Ground
(1)
................... –2.0V to +13.5V
V
PP
with Respect to Ground
during Program/Erase
(1)
.............. –0.6V to +14.0V
V
CC
with Respect to Ground
(1)
............ –2.0V to +7.0V
Package Power Dissipation
Capability (T
A
= 25°C) .................................. 1.0 W
Lead Soldering Temperature (10 secs) ............ 300°C
Output Short Circuit Current
(2)
........................ 100 mA
RELIABILITY CHARACTERISTICS
Symbol
N
END(3)
T
DR(3)
V
ZAP(3)
I
LTH(3)(4)
Parameter
Endurance
Data Retention
ESD Susceptibility
Latch-Up
Min.
100K
10
2000
100
Max.
*COMMENT
Stresses above those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
These are stress ratings only, and functional operation of
the device at these or any other conditions outside of those
listed in the operational sections of this specification is not
implied. Exposure to any absolute maximum rating for
extended periods may affect device performance and
reliability.
Units
Cycles/Byte
Years
Volts
mA
Test Method
MIL-STD-883, Test Method 1033
MIL-STD-883, Test Method 1008
MIL-STD-883, Test Method 3015
JEDEC Standard 17
CAPACITANCE
T
A
= 25°C, f = 1.0 MHz
Limits
Symbol
C
IN(3)
C
OUT(3)
C
VPP(3)
Test
Input Pin Capacitance
Output Pin Capacitance
V
PP
Supply Capacitance
Min
Max.
6
10
25
Units
pF
pF
pF
Conditions
V
IN
= 0V
V
OUT
= 0V
V
PP
= 0V
Note:
(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC
voltage on output pins is V
CC
+0.5V, which may overshoot to V
CC
+ 2.0V for periods of less than 20ns.
(2) Output shorted for no more than one second. No more than one output shorted at a time.
(3) This parameter is tested initially and after a design or process change that affects the parameter.
(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V
CC
+1V.
3
Doc. No. 1014, Rev. A
CAT28F102
D.C. OPERATING CHARACTERISTICS
V
CC
= +5V
±10%,
unless otherwise specified
Main Menu
Limits
Symbol
I
LI
I
LO
I
SB1
I
SB2
I
CC1
I
CC2(1)
I
CC3(1)
I
CC4(1)
I
PPS
I
PP1
I
PP2(1)
I
PP3(1)
I
PP4(1)
V
IL
V
ILC
V
OL
V
IH
V
IHC
V
OH1
V
OH2
V
ID
I
ID(1)
V
LO
Parameter
Input Leakage Current
Output Leakage Current
V
CC
Standby Current CMOS
V
CC
Standby Current TTL
V
CC
Active Read Current
V
CC
Programming Current
V
CC
Erase Current
V
CC
Prog./Erase Verify Current
V
PP
Standby Current
V
PP
Read Current
V
PP
Programming Current
V
PP
Erase Current
V
PP
Prog./Erase Verify Current
Input Low Level TTL
Input Low Level CMOS
Output Low Level
Input High Level TTL
Input High Level CMOS
Output High Level TTL
Output High Level CMOS
A
9
Signature Voltage
A
9
Signature Current
V
CC
Erase/Prog. Lockout Voltage
2.5
2
V
CC
*0.7
2.4
V
CC
-0.4
11.4
13.0
200
–0.5
–0.5
Min.
Max.
±1
±1
100
1
50
30
30
30
±10
100
50
30
5
0.8
0.8
0.45
V
CC
+0.5
V
CC
+0.5
Unit
µA
µA
µA
mA
mA
mA
mA
mA
µA
µA
mA
mA
mA
V
V
V
V
V
V
V
V
µA
V
I
OH
= –2.5mA, V
CC
= 4.5V
I
OH
= –400µA, V
CC
= 4.5V
A
9
= V
ID
A
9
= V
ID
I
OL
= 5.8mA, V
CC
= 4.5V
Test Conditions
V
IN
= V
CC
or V
SS
V
CC
= 5.5V, OE = V
IH
V
OUT
= V
CC
or V
SS
,
V
CC
= 5.5V, OE = V
IH
CE = V
CC
±0.5V,
V
CC
= 5.5V
CE = V
IH
, V
CC
= 5.5V
V
CC
= 5.5V, CE = V
IL
,
I
OUT
= 0mA, f = 6 MHz
V
CC
= 5.5V,
Programming in Progress
V
CC
= 5.5V,
Erasure in Progress
V
CC
= 5.5V, Program or
Erase Verify in Progress
V
PP
= V
PPL
V
PP
= V
PPH
V
PP
= V
PPH
,
Programming in Progress
V
PP
= V
PPH
,
Erasure in Progress
V
PP
= V
PPH
, Program or
Erase Verify in Progress
Supply Characteristics
V
CC
V
PPL
V
PPH
V
CC
Supply Voltage
V
PP
During Read Operations
V
PP
During Read/Erase/Program
4.5
0
11.4
5.5
6.5
12.6
V
V
V
Doc. No. 1014, Rev. A
4
Main Menu
A.C. CHARACTERISTICS, Read Operation
V
CC
= +5V
±10%,
unless otherwise specified
JEDEC
Symbol
t
AVAV
t
ELQV
t
AVQV
t
GLQV
t
AXQX
t
GLQX
t
ELQX
t
GHQZ
t
EHQZ(1)(2)
t
WHGL
Standard
Symbol
Parameter
t
RC
t
CE
t
ACC
t
OE
t
OH
t
OLZ(1)(6)
t
LZ(1)(6)
t
DF(1)(2)
-
Read Cycle Time
CE
Access Time
Address Access Time
OE
Access Time
Output Hold from Address
OE/CE
Chan
OE
to Output in Low-Z
CE
to Output in Low-Z
OE
High to Output High-Z
CE
High to Output High-Z
Write Recovery Time Before
Read
6
0
0
0
25
35
28F102- 10
(7)
Min.
Max.
100
100
100
45
0
0
0
30
40
28F102- 12
Min.
Max.
120
120
120
50
CAT28F102
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
Figure 1. A.C. Testing Input/Output Waveform
(3)(4)(5)
2.4 V
INPUT PULSE LEVELS
0.45 V
0.8 V
2.0 V
REFERENCE POINTS
Figure 2. A.C. Testing Load Circuit (example)
1.3V
1N914
3.3K
DEVICE
UNDER
TEST
OUT
CL = 100 pF
CL INCLUDES JIG CAPACITANCE
Note:
(1) This parameter is tested initially and after a design or process change that affects the parameter.
(2) Output floating (High-Z) is defined as the state where the external data line is no longer driven by the output buffer.
(3) Input Rise and Fall Times (10% to 90%) < 10 ns.
(4) Input Pulse Levels = 0.45V and 2.4V. For high speed input pulse levels 0.0V and 3.0V.
(5) Input and Output Timing Reference = 0.8V and 2.0V. For high speed input and output timing reference=1.5V.
(6) Low-Z is defined as the state where the external data may be driven by the output buffer but may not be valid.
(7) For Load and Reference Points see Figures 1 and 2
5
Doc. No. 1014, Rev. A
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