CAT24C02, CAT24C04,
CAT24C08, CAT24C16
EEPROM Serial
2/4/8/16 Kb I
2
C
Description
The CAT24C02/04/08/16 are 2−Kb, 4−Kb, 8−Kb and 16−Kb
respectively I
2
C Serial EEPROM devices organized internally as
16/32/64 and 128 pages respectively of 16 bytes each. All devices
support both the Standard (100 kHz) as well as Fast (400 kHz) I
2
C
protocol.
Data is written by providing a starting address, then loading 1 to 16
contiguous bytes into a Page Write Buffer, and then writing all data to
non−volatile memory in one internal write cycle. Data is read by
providing a starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address up to eight
CAT24C02, four CAT24C04, two CAT24C08 and one CAT24C16
device on the same bus.
Features
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SOIC−8 WIDE
X SUFFIX
CASE 751BE
UDFN8−EP
HU4 SUFFIX
CASE 517AZ
TSSOP−8
Y SUFFIX
CASE 948AL
TSOT−23
TD SUFFIX
CASE 419AE
•
•
•
•
•
•
•
•
•
•
Supports Standard and Fast I
2
C Protocol
1.7 V to 5.5 V Supply Voltage Range
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I
2
C Bus Inputs
(SCL and SDA)
Low power CMOS Technology
More than 1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SOIC−8
W SUFFIX
CASE 751BD
WLCSP−5**
C5A SUFFIX
CASE 567DD
WLCSP−4**
C4A SUFFIX
CASE 567DC
WLCSP−4**
C4U SUFFIX
CASE 567NX
** WLCSP are available for the CAT24C04,
CAT24C08 and CAT24C16 only.
For serial EEPROM in the US8 package, please
consult the N24C02 datasheet
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 18 of this data sheet.
This document contains information on some products that are still under development.
ON Semiconductor reserves the right to change or discontinue these products without
notice.
©
Semiconductor Components Industries, LLC, 2016
October, 2018
−
Rev. 34
1
Publication Order Number:
CAT24C01/D
CAT24C02, CAT24C04, CAT24C08, CAT24C16
PIN CONFIGURATIONS AND MARKING INFORMATION
V
CC
Table 1. PIN FUNCTION
Pin Name
†
Function
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
Power Supply
Ground
No Connect
A0, A1, A2
SDA
SCL
A
2
, A
1
, A
0
WP
CAT24Cxx
SDA
SCL
WP
V
CC
V
SS
NC
V
SS
Figure 1. Functional Symbol
CAT24C__
16 / 08 / 04 / 02
NC / NC / NC / A
0
NC / NC / A
1
/ A
1
NC / A
2
/ A
2
/ A
2
V
SS
†The exposed pad for the UDFN packages can be left floating or
connected to Ground.
Pin 1
1
2
3
4
8
7
6
5
V
CC
WP
SCL
SDA
B
A
1
V
CC
2
V
SS
Pin 1
1
V
CC
2
3
V
SS
A
B
SCL
C
SDA
SCL
SDA
WP
SOIC (W, X), TSSOP (Y),
UDFN−EP (HU4) (Top View)
WLCSP−4***
(Top Views)
WLCSP−5***
*** WLCSP are available for the CAT24C04,
CAT24C08 and CAT24C16 only.
TOP MARKING FOR WLCSP
(Ball Down)
SCL
V
SS
SDA
1
2
3
4
V
CC
X
YM
WLCSP−4
(C4A)
X
YW
WLCSP−4
(C4U)
X = Specific Device
X =
Code
4 or R = 24C04
8 or T = 24C08
6 or V = 24C16
Y = Production Year (Last Digit)
M = Production Month (1−9, O, N, D)
W = Production Week
X
YM
WLCSP−5
5
WP
Pin 1
Pin 1
Pin 1
TSOT−23 (TD) (Top View)
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2
CAT24C02, CAT24C04, CAT24C08, CAT24C16
Table 2. ABSOLUTE MAXIMUM RATINGS
Parameters
Storage Temperature
Voltage on any pin with respect to Ground (Note 1)
Ratings
−65
to +150
−0.5
to +6.5
Units
°C
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During input transitions, voltage undershoot on any pin should not exceed
−1
V for more than 20 ns. Voltage overshoot on pins A
0
, A
1
, A
2
and WP should not exceed V
CC
+ 1 V for more than 20 ns, while voltage on the I
2
C bus pins, SCL and SDA, should not exceed the absolute
maximum ratings, irrespective of V
CC
.
Table 3. RELIABILITY CHARACTERISTICS
(Note 2)
Symbol
N
END
(Note 3)
T
DR
Endurance
Data Retention
Parameter
Min
1,000,000
100
Units
Program / Erase Cycles
Years
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, V
CC
= 5 V, 25°C.
Table 4. D.C. OPERATING CHARACTERISTICS
Symbol
I
CCR
I
CCW
I
SB
Parameter
Read Current
Write Current
Standby Current
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +125°C and V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Test Conditions
Read, f
SCL
= 400 kHz
Write, f
SCL
= 400 kHz
All I/O Pins at GND or V
CC
T
A
=
−40°C
to +85°C
V
CC
≤
3.3 V
T
A
=
−40°C
to +85°C
V
CC
> 3.3 V
T
A
=
−40°C
to +125°C
I
L
V
IL
V
IH
V
OL
I/O Pin Leakage
Input Low Voltage
Input High Voltage
A
0
, A
1
, A
2
and WP
SCL and SDA
Output Low
Voltage
V
CC
> 2.5 V, I
OL
= 3 mA
V
CC
< 2.5 V, I
OL
= 1 mA
Pin at GND or V
CC
−0.5
0.7 x V
CC
0.7 x V
CC
Min
Max
1
2
1
3
5
2
0.3 x V
CC
V
CC
+ 0.5
5.5
0.4
0.2
mA
V
V
Units
mA
mA
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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3
CAT24C02, CAT24C04, CAT24C08, CAT24C16
Table 5. PIN IMPEDANCE CHARACTERISTICS
(V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +125°C and V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Symbol
C
IN
(Note 4)
I
WP
(Note 5)
Parameter
SDA Pin Capacitance
Other Pins
WP Input Current
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.7 V
V
IN
> V
IH
I
A
(Note 5)
Address Input Current
(A0, A1, A2)
Product Rev H: CAT24C02
Product Rev K: CAT24C04,
CAT24C08, CAT24C16
V
IN
< V
IH
, V
CC
= 5.5 V
V
IN
< V
IH
, V
CC
= 3.3 V
V
IN
< V
IH
, V
CC
= 1.7 V
V
IN
> V
IH
Conditions
V
IN
= 0 V, f = 1.0 MHz, V
CC
= 5.0 V
Max
8
6
130
120
80
2
50
35
25
2
mA
Units
pF
pF
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is
relatively strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To
conserve power, as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak
current source.
Table 6. A.C. CHARACTERISTICS
(Note 6) (V
CC
= 1.8 V to 5.5 V, T
A
=
−40°C
to +125°C and V
CC
= 1.7 V to 5.5 V, T
A
=
−40°C
to +85°C, unless otherwise specified.)
Standard
Symbol
F
SCL
t
HD:STA
t
LOW
t
HIGH
t
SU:STA
t
HD:DAT
t
SU:DAT
t
R
t
F
(Note 6)
t
SU:STO
t
BUF
t
AA
t
DH
T
i
(Note 6)
t
SU:WP
t
HD:WP
t
WR
t
PU
(Notes 7, 8)
6.
7.
8.
Clock Frequency
START Condition Hold Time
Low Period of SCL Clock
High Period of SCL Clock
START Condition Setup Time
Data In Hold Time
Data In Setup Time
SDA and SCL Rise Time
SDA and SCL Fall Time
STOP Condition Setup Time
Bus Free Time Between STOP and START
SCL Low to Data Out Valid
Data Out Hold Time
Noise Pulse Filtered at SCL and SDA Inputs
WP Setup Time
WP Hold Time
Write Cycle Time
Power−up to Ready Mode
0
2.5
5
1
100
100
0
2.5
5
1
4
4.7
3.5
100
100
4
4.7
4
4.7
0
250
1000
300
0.6
1.3
0.9
Parameter
Min
Max
100
0.6
1.3
0.6
0.6
0
100
300
300
Min
Fast
Max
400
Units
kHz
ms
ms
ms
ms
ms
ns
ns
ns
ms
ms
ms
ns
ns
ms
ms
ms
ms
Test conditions according to “AC Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
t
PU
is the delay between the time V
CC
is stable and the device is ready to accept commands.
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CAT24C02, CAT24C04, CAT24C08, CAT24C16
Table 7. A.C. TEST CONDITIONS
Input Drive Levels
Input Rise and Fall Time
Input Reference Levels
Output Reference Level
Output Test Load
0.2 x V
CC
to 0.8 x V
CC
v
50 ns
0.3 x V
CC
, 0.7 x V
CC
0.5 x V
CC
Current Source I
OL
= 3 mA (V
CC
w
2.5 V); I
OL
= 1 mA (V
CC
< 2.5 V); C
L
= 100 pF
Power−On Reset (POR)
Each CAT24Cxx* incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state.
A CAT24Cxx device will power up into Standby mode
after V
CC
exceeds the POR trigger level and will power
down into Reset mode when V
CC
drops below the POR
trigger level. This bi−directional POR feature protects the
device against ‘brown−out’ failure following a temporary
loss of power.
*For common features, the CAT24C02/04/08/16 will be
referred to as CAT24Cxx.
Pin Description
SCL:
The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA:
The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this pin
is open drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL.
A0, A1 and A2:
The Address inputs set the device address
when cascading multiple devices. When not driven, these
pins are pulled LOW internally.
WP:
The Write Protect input pin inhibits all write
operations, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
Functional Description
The CAT24Cxx supports the Inter−Integrated Circuit
2
C) Bus data transmission protocol, which defines a device
(I
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by a
Master device, which generates the serial clock and all
START and STOP conditions. The CAT24Cxx acts as a
Slave device. Master and Slave alternate as either
transmitter or receiver.
The I
2
C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the V
CC
supply via pull−up
resistors. Master and Slave devices connect to the 2−wire
bus via their respective SCL and SDA pins. The transmitting
device pulls down the SDA line to ‘transmit’ a ‘0’ and
releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see AC Characteristics).
I
2
C Bus Protocol
During data transfer, the SDA line must remain stable
while the SCL line is high. An SDA transition while SCL is
high will be interpreted as a START or STOP condition
(Figure 2). The START condition precedes all commands. It
consists of a HIGH to LOW transition on SDA while SCL
is HIGH. The START acts as a ‘wake−up’ call to all
receivers. Absent a START, a Slave will not respond to
commands. The STOP condition completes all commands.
It consists of a LOW to HIGH transition on SDA while SCL
is HIGH.
NOTE:
The I/O pins of CAT24Cxx do not obstruct the SCL
and SDA lines if the VCC supply is switched off. During
power−up, the SCL and SDA pins (connected with pull−up
resistors to VCC) will follow the VCC monotonically from
VSS (0 V) to nominal VCC value, regardless of pull−up
resistor value. The delta between the VCC and the
instantaneous voltage levels during power ramping will be
determined by the relation between bus time constant
(determined by pull−up resistance and bus capacitance) and
actual VCC ramp rate.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. For normal Read/Write operations, the
first 4 bits of the Slave address are fixed at 1010 (Ah). The
next 3 bits are used as programmable address bits when
cascading multiple devices and/or as internal address bits.
The last bit of the slave address, R/W, specifies whether a
Read (1) or Write (0) operation is to be performed. The 3
address space extension bits are assigned as illustrated in
Figure 3. A
2
, A
1
and A
0
must match the state of the external
address pins, and a
10
, a
9
and a
8
are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 4). The Slave will also
acknowledge the address byte and every data byte presented
in Write mode. In Read mode the Slave shifts out a data byte,
and then releases the SDA line during the 9
th
clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 5.
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