Crystal connection or external reference clock input.
Crystal connection. If using an external reference, this pin must be left unconnected.
Power supply for the core
Power supply for the output buffers.
Ground connection for the output buffers
Ground connection
48MHz Clock Output
12MHz Clock Output
33.3 MHz low EMI Clock Output
33.3 MHz low EMI Clock Output
Selection Bit for Programmable Clock. To be Pulled HIGH or LOW suitably.
See the PCLK Selection Table for details
66.6 MHz low EMI Clock Output
66.6 MHz low EMI Clock Output
Selection Bit for Programmable Clock. To be Pulled HIGH or LOW suitably.
See the PCLK Selection Table for details
Programmable Clock Output
25 MHz low EMI Clock Output
Rev. 1 | Page 2 of 8 | www.onsemi.com
ASM3P2854C
PCLK Selection Table
S2
0
0
1
1
S1
0
1
0
1
Programmable Clock (MHz)
24.00448
21.33732
21.19962
20.40464
Absolute Maximum Ratings
Symbol
VDD,
VDD_FOUT
T
STG
T
s
T
J
T
DV
Parameter
Rating
-0.5 to +4.6
-65 to +125
260
150
2
Unit
V
°
C
°
C
°
C
KV
Voltage on any pin with respect to Ground
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22- A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Recommended Operating Conditions
Symbol
T
A
VDD
VDD_FOUT
Parameter
Operating Temperature
Core Voltage
Output Buffer Voltage
Min
0
+3.0
+3.0
Typ
+3.3
+3.3
Max
+70
+3.6
+3.6
Units
°
C
V
V
Rev. 1 | Page 3 of 8 | www.onsemi.com
ASM3P2854C
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
I
XOL
I
XOH
V
OL
V
OH
I
DD
I
CC
VDD
VDD_FOUT
t
ON
Z
O
Input low voltage
Input high voltage
Input low current
Input high current
XOUT output low current (V
XOL
@ 0.4V, VDD = 3.3V)
XOUT output high current (V
XOH
@ 2.5V, VDD = 3.3V)
Output low voltage (VDD = 3.3V, I
OL
= 10mA)
Output high voltage (VDD = 3.3V, I
OH
= -10mA)
Static supply current
1
Parameter
Min
GND-0.3
2.0
Typ
Max
0.8
VDD+0.3
-35
35
Unit
V
V
µA
µA
mA
mA
3
3
0.4
2.5
15
33
3.0
3.0
3.3
3.3
30
3.6
3.6
5
V
V
mA
mA
V
V
mS
Dynamic supply current ( VDD=3.3V, No Load)
Operating Core Voltage
Operating Output Buffer Voltage
Power-up time (first locked cycle after power-up)
Output impedance
2
Notes: 1. XIN / CLKIN pin is pulled to GND.
2. VDD and CLKIN inputs are stable.
Rev. 1 | Page 4 of 8 | www.onsemi.com
ASM3P2854C
AC Electrical Characteristics
Symbol
XIN / CLKIN
Input frequency
At Pin 7
At Pin 8
F
OUT
Output frequency
At Pins 9 and 10
At Pins 12 and 13
At Pin 15
At Pin 16
f
d
t
LH
t
HL
2
2
1
Parameter
Min
Typ
24
48
12
33
66
PCLK
25
-0.5
1.0
1.0
±300
Max
Unit
MHz
Frequency Deviation for Spread Spectrum Clocks
Output rise time (measured from 20% to 80%)
Output fall time (measured from 80% to 20%)
Cycle to Cycle Jitter (For Modulated Clocks);
unloaded outputs
Period Jitter (For Non-Modulated Clocks) );
unloaded outputs
Output duty cycle
45
%
nS
t
JC
t
JP
t
D
±275
50
55
pS
%
Notes: 1. See the PCLK Selection Table for PCLK Frequency.
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
