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ASM3P2474A

产品描述Peak EMI Reducing Solution
文件大小189KB,共7页
制造商ON Semiconductor(安森美)
官网地址http://www.onsemi.cn
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ASM3P2474A概述

Peak EMI Reducing Solution

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ASM3P2474A
Peak EMI
Reducing Solution
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V Supply.
Operating current less than 6mA.
CMOS design.
Input frequency range : 13MHz to 30MHz
Generates a 1X and 2X low EMI spread
spectrum clock of the input frequency.
Output Frequency Selection through FSEL pin
Frequency deviation : -1.5% (Typ) @25MHz
-1.5% (Typ) @50MHz
Available in 6L-TSOP (6L-TSOT-23) package.
The ASM3P2474A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2474A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
Applications
The ASM3P2474A is targeted towards all portable
devices like MP3 players and digital still cameras.
Product Description
The ASM3P2474A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2474A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2474A allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads and shielding that are
traditionally required to pass EMI regulations.
Key Specifications
Description
Supply voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency
Deviation
FSEL=0
FSEL=1
Specification
VDD = 3.3V ± 0.3V
±200pS (Typ)
45/55% (worst case)
F
IN
/640
-1.5% (Typ) @ 50MHz
-1.5% (Typ) @ 25MHz
Block Diagram
VDD
FSEL
Modulation
XIN / CLKIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
©2010 SCILLC. All rights reserved.
OCTOBER 2010 – Rev. 2.1
Publication Order Number:
ASM3P2474/D

 
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