ASM3P2182A
LCD Panel EMI Reduction IC
Features
•
FCC approved method of EMI attenuation.
•
Provides up to 15dB EMI reduction.
•
Generates a 1X low EMI spread spectrum clock of
the input frequency.
•
Input frequency range: 25MHz to 210MHz.
•
Internal loop filter minimizes external components
and board space.
•
Center spread.
•
4 spread frequency deviation selections: ± 0.13% to
± 1.24%.
•
Low inherent Cycle-to-cycle jitter.
•
3.3V Operating Voltage.
•
TTL or CMOS compatible inputs and outputs.
•
Low power CMOS design.
•
Supports notebook VGA and other LCD timing
controller applications.
The ASM3P2182A reduces electromagnetic interference
(EMI) at the clock source, allowing system wide
reduction of EMI of down stream clock and data
dependent signals. The ASM3P2182A allows significant
system cost savings by reducing the number of circuit
board layers ferrite beads, shielding and other passive
components that are traditionally required to pass EMI
regulations.
The ASM3P2182A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The ASM3P2182A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized
clock, and more importantly, decreases the peak
amplitudes of its harmonics. This results in significantly
lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency
generators. Lowering EMI by increasing a signal’s
bandwidth is called ‘spread spectrum clock generation.’
•
Available in 8-pin SOIC Package.
Product Description
The ASM3P2182A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of input clock frequencies from 25MHz to 210MHz.
(Refer
to
Input Frequency and Modulation Rate Table).
The ASM3P2182A can generate an EMI reduced clock
from an OSC or a system generated clock. The
ASM3P2182A offers a Center Spread clock and with a
percentage deviation from ± 0.13% or ± 1.24%.
FS0
FS1
S0
Applications
The ASM3P2182A is targeted towards EMI management
for memory and LVDS interfaces in mobile graphic
chipsets and high-speed digital applications such as PC
peripheral
devices,
consumer
electronics,
and
embedded controller systems.
V
DD
Modulation
CLKIN
Crystal
Oscillato
r
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
©2010 SCILLC. All rights reserved.
OCTOBER 2010 – Rev.
2.1
Publication Order Number:
ASM3P2182/D
ASM3P2182A
Pin Configuration
CLKIN 1
GND 2
ASM3P2182A
S1 3
S0 4
8 FS1
7 FS0
6 VDD
5 ModOUT
Pin Description
Pin#
Pin Name
1
2
3
4
5
6
7
8
CLKIN
GND
S1
S0
ModOUT
VDD
FS0
FS1
Type
I
P
I
I
O
P
I
I
Description
Connect to externally generated clock signal.
Ground to entire chip.
Spread range select. Digital logic input used to select frequency deviation
(Refer to
Spread Deviation Table).
This pin has an internal pull-up resistor.
Spread range select. Digital logic input used to select frequency deviation
(Refer to
Spread Deviation Table).
This pin has an internal pull-up resistor.
Spread spectrum low EMI output.
Power supply for the entire chip (3.3V).
Frequency range select. Digital logic input used to select frequency range
(Refer to
Input Frequency and Modulation Rate Table).
This pin has an internal pull-up resistor.
Frequency range select. Digital logic input used to select frequency range
(Refer to
Input Frequency and Modulation Rate Table).
This pin has an internal pull-up resistor.
Input Frequency and Modulation Rate table
FS1 (pin 8)
0
0
1
1
FS0 (pin 7)
0
1
0
1
Frequency Range
25MHz to 50MHz
50MHz to 103MHz
75MHz to 150MHz
160MHz to 210MHz
Rev. 2 | Page 2 of 6 | www.onsemi.com
ASM3P2182A
Spread Deviation Selection table
S1
0
0
1
1
S0
0
1
0
1
25
MHz
0.28
0.8
1.2
2.1
40
MHz
0.19
0.3
0.54
1.0
65
MHz
0.15
0.3
0.45
1.1
Spreading Range (± %)
1
2
81
81
108
MHz
MHz
MHz
0.12
0.2
0.4
0.9
0.18
0.5
0.8
1.4
0.15
0.3
0.6
1.1
120
MHz
0.1
0.19
0.36
0.75
162
MHz
0.1
0.3
1.0
1.9
200
MHz
0.06
0.1
0.6
1.2
Notes: 1. Frequency Range- 50MHz to 103MHz
2. Frequency Range- 75MHz to 150MHz
Absolute Maximum Ratings
Symbol
VDD
V
IN
V
OUT
T
STG
T
s
T
J
T
DV
Parameter
Rating
-0.5 to +4.6
VSS-0.5 to VDD+0.5
VSS-0.5 to VDD+0.5
-55 to +125
260
150
2
Unit
V
V
V
°
C
°
C
°
C
KV
Supply Voltage pin with respect to Ground
Input Voltage pin with respect to Ground
Output Voltage pin with respect to Ground
Storage temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage (As per JEDEC STD22-A114-B)
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Recommended Operating Conditions
Parameter
VDD
T
A
C
L
C
IN
Operating Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance
Input Capacitance
5
Description
Min
2.7
-40
Typ
3.3
Max
3.7
+85
15
Unit
V
°
C
pF
pF
Rev. 2 | Page 3 of 6 | www.onsemi.com
ASM3P2182A
DC Electrical Characteristics
Symbol
Parameter
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
CC
I
DD
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Output low voltage (V
DD
= 3.3V, I
OL
= 20mA)
Output high voltage (V
DD
= 3.3V, I
OH
= 20mA)
Dynamic supply current
Normal mode (3.3V and 10pF loading)
Static supply current
1
Standby mode
Operating voltage
Power up time
(first locked clock cycle after power up)
Clock out impedance
2.5
8.46
12
0.6
2.7
3.3
0.18
50
3.7
17.78
Min
GND – 0.3
2.0
Typ
Max
0.8
V
DD
+ 0.3
-35
35
0.4
Unit
V
V
µA
µA
V
V
mA
mA
V
mS
Note: 1. CLKIN pin is pulled low.
AC Electrical Characteristics
Symbol
CLKIN
ModOUT
t
LH
t
HL
1
1
Parameter
Input frequency
Output frequency
Output rise time (measured at 0.8V to 2.0V)
Output fall time (measured at 2.0V to 0.8V)
Jitter (cycle to cycle)
Output duty cycle
Min
25
25
1.2
0.8
Typ
Max
210
210
Unit
MHz
MHz
nS
nS
pS
%
1.32
0.9
1.4
1.0
±360
t
JC
T
D
45
50
55
Note: 1. t
LH
and t
HL
are measured into a capacitive load of 15pF.
Rev. 2 | Page 4 of 6 | www.onsemi.com
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