MK2308-1H
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Description
The MK2308-1H is a low phase noise, high-speed PLL
based, 8-output, low skew zero delay buffer. Based on
ICS’ proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides eight low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly
from the input (for testing), and can be set to tri-state
mode or to stop at a low level. For normal operation as
a zero delay buffer, any output clock is tied to the FBIN
pin.
ICS manufactures a large variety of clock generators
and buffers.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
Clock outputs from 10 to 133 MHz
Zero input-output delay
Eight low skew (<200 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 25 mA output drive
capability at TTL levels
5 V tolerant FBIN and CLKIN pins
Tri-state mode for board-level testing
Advanced, low-power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature range available
Packaged in 16-pin SOIC and TSSOP packages
Available in Pb (lead) free package
Industrial and commercial temp operation
Block Diagram
VDD
2
2
Control
Logic
S2, S1
CLKA1
CLKA2
CLKIN
CLKA3
CLKA4
FBIN
Clock
Synthesis
PLL
1
0
CLKB1
CLKB2
CLKB3
CLKB4
GND
2
Feedback is shown from CLKB4 for
illustration, but may come from any output.
MDS 2308-1H C
I n t e gra te d C i r c u i t S y s t e m s
●
1
525 Race Stre et, San Jo se, CA 9 5126
●
Revision 020905
te l (40 8) 2 97-12 01
●
w w w. i c st . c o m
MK2308-1H
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Pin Assignment
CLKIN
CLKA1
CLKA2
VDD
GND
CLKB1
CLKB2
S2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FBIN
CLKA4
CLKA3
VDD
GND
CLKB4
CLKB3
S1
16-pin narrow (150 mil) SOIC and
(173 mil) TSSOP
Output Clock Mode Select Table
S2
0
0
1
1
S1
0
1
0
1
CLKA1:A4
Tri-state (note 1)
Running
Running
Running
CLKB1:B4
Tri-state (note 1)
Tri-state (note 1)
Running
Running
A & B Source
PLL
PLL
CLKIN (note 2)
PLL
PLL Status
OFF
ON
OFF
ON
Note 1. Outputs are in high impedance state
Note 2. Buffer mode only; not zero delay between input and output
Pin Descriptions
Pin
Number
1
2-3
4
5
6-7
8
9
10 - 11
12
13
14 - 15
16
Pin
Name
CLKIN
CLKA1:A4
VDD
GND
CLKB1:B4
S2
S1
CLKB1:B4
GND
VDD
CLKA1:A4
FBIN
Pin Type
Input
Output
Power
Power
Output
Input
Input
Output
Power
Power
Output
Input
Clock input (5 V tolerant).
Clock outputs A1:A4. See table above.
Power supply. Connect to 3.3 V.
Connect to ground.
Clock outputs B1:B4. See table above.
Select input 2. See table above. Internal pull-up.
Select input 1. See table above. Internal pull-up.
Clock outputs B1:B4. See table above.
Connect to ground.
Power supply. Connect to 3.3 V.
Clock outputs A1:A4. See table above.
Feedback input. Connect to any output under normal operation (5 V tolerant).
Pin Description
MDS 2308-1H C
In te grated Circuit Systems
●
2
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2308-1H
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
External Components
The MK2308-1H requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01 mF should be connected between VDD and GND on pins 4 and 5, and VDD and GND
on pins 13 and 12, as close to the device as possible. A series termination resistor of 33Ω may be used to
each clock output pin to reduce reflections.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the MK2308-1H. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Supply Voltage, VDD
All Inputs and Outputs
CLKIN and FBIN inputs
Electrostatic Discharge
Ambient Operating Temperature
Industrial Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
7V
Rating
-0.5 V to VDD+0.5 V
-0.5 V to 5.5 V
2000 V
0 to +70°C
-40 to +85°C
-65 to +150°C
150°C
260°C
Recommended Operation Conditions
Parameter
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Min.
-40
+3.0
Typ.
Max.
+85
+3.6
Units
°C
V
DC Electrical Characteristics
VDD=3.3 V ±10%,
Ambient temperature -40 to +85°C (Industrial), 0 to 70°C (Commercial)
Parameter
Operating Voltage
Input High Voltage
Input Low Voltage
Input Low Current
Input High Current
Output High Voltage
Output Low Voltage
Symbol
VDD
V
IH
V
IL
I
IL
I
IH
V
OH
V
OL
Conditions
Min.
3.0
2
Typ.
Max.
3.6
0.8
Units
V
V
V
µA
µA
V
V
VIN = 0V
VIN = VDD
I
OH
= -12 mA
I
OL
= 12 mA
2.4
50
100
0.4
MDS 2308-1H C
In te grated Circuit Systems
●
3
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2308-1H
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Parameter
Output High Voltage,
CMOS level
Operating Supply Current
Power Down Supply
Current
Short Circuit Current
Input Capacitance
Symbol
V
OH
IDD
IDDPD
I
OS
C
IN
Conditions
I
OH
= -4 mA
No Load, S2 = 1, S1 = 1,
Note 1
CLKIN = 0, S2 = 0, S1 = 1
CLKIN = 0, Note 2
Each output
S2, S1, FBIN
Min.
VDD-0.4
Typ.
Max.
Units
V
70
12
12
±70
5
mA
µA
µA
mA
pF
AC Electrical Characteristics
VDD = 3.3 V ±10%,
Ambient Temperature -40 to +85°C (Industrial), 0 to 70°C (Commercial)
Parameter
Input Clock Frequency
Output Clock Frequency
Output Rise Time
Output Fall Time
Output Clock Duty Cycle
Device to Device Skew
Output to Output Skew
Input to Output Skew
Maximum Absolute JItter
Cycle to Cycle Jitter
Symbol
f
IN
t
OR
t
OF
t
DC
Conditions
See table on page 2
See table on page 2
0.8 to 2.0V, CL=30pF
2.0 to 0.8V, CL=30pF
measured at VDD/2
rising edges at VDD/2
rising edges at VDD/2
rising edges at VDD/2, FBIN to
CLKA4, S1 = 1, S0 = 1, Note 1
CL=15 pF, measured at 66.67M
CL=30 pF, measured at 66.67M
CL=15 pF, measured at 66.67M
CL=15 pF, measured at 133.33M
Min.
10
10
Typ.
Max. Units
133
133
1.5
1.25
MHz
MHz
ns
ns
%
ps
ps
ps
ps
200
200
100
1.0
ps
ps
ps
ms
45
50
55
700
200
±250
130
PLL Lock Time
Note 3
Note 1: With CLKIN = 100 MHz, FBIN to CLKA4, all outputs at 100 MHz
Note 2: When there is no clock signal present at CLKIN, the MK2308-1H will enter power down mode. The
PLL is stopped and the outputs are tri-state.
Note 3: With VDD at a steady rate and valid clocks at CLKIN and FBIN
Thermal Characteristics 16TSSOP
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
78
70
68
37
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
MDS 2308-1H C
In te grated Circuit Systems
●
4
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
MK2308-1H
3.3 V
OLT
Z
ERO
D
ELAY
, L
OW
S
KEW
B
UFFER
Thermal Characteristics 16SOIC
Parameter
Thermal Resistance Junction to
Ambient
Symbol
θ
JA
θ
JA
θ
JA
θ
JC
Conditions
Still air
1 m/s air flow
3 m/s air flow
Min.
Typ.
120
115
105
58
Max. Units
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Case
Package Outline and Package Dimensions
(16-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Symbol
Min
Max
Inches
Min
Max
16
E
INDEX
AREA
H
1 2
D
A
A1
B
C
D
E
e
H
h
L
α
1.35
1.75
0.10
0.25
0.33
0.51
0.19
0.25
9.80
10.00
3.80
4.00
1.27 BASIC
5.80
6.20
0.25
0.50
0.40
1.27
0
°
8
°
.0532
.0688
.0040
.0098
.013
.020
.0075
.0098
.3859
.3937
.1497
.1574
0.050 BASIC
.2284
.2440
.010
.020
.016
.050
0
°
8
°
A
A1
h x 45
C
-C-
e
B
SEATING
PLANE
L
.10 (.004)
C
MDS 2308-1H C
In te grated Circuit Systems
●
5
525 Ra ce Street, San Jose, CA 9512 6
●
Revision 020905
tel (4 08) 297-1 201
●
w w w. i c s t . c o m
嵌入式系统
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