HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
3.3 V 168-pin Registered SDRAM Modules
PC133 128 MByte Module
PC133 256 MByte module
PC133 512 MByte Module
PC133 1 GByte Module
PC133 2 GByte Module
• 168-pin Registered 8 Byte Dual-In-Line
SDRAM Module for PC and Server main
memory applications
• One bank 16M
×
72, 32M x 72, 64M
×
72and
128M x 72, two bank 128M
×
72 and
256M x 72 organization
• Optimized for ECC applications with very low
input capacitances
• JEDEC standard Synchronous DRAMs
(SDRAM) Programmable CAS Latency, Burst
Length and Wrap Sequence (Sequential &
Interleave)
• Single + 3.3 V (
±
0.3 V) power supply
• Auto Refresh (CBR) and Self Refresh
• Performance:
speed grade
f
CK
t
CK
t
AC
f
CK
t
CK
t
AC
Clock Frequency (max.) @ CL = 3
Clock Cycle Time (min.) @ CL = 3
Clock Access Time (min.) @ CL= 3
Clock Frequency (max.) @ CL = 2
Clock Cycle Time (min.) @ CL = 2
Clock Access Time (min.) @ CL= 2
• Programmable CAS Latency, Burst Length,
and Wrap Sequence (Sequential &
Interleave)
• All inputs and outputs are LVTTL compatible
• Serial Presence Detect with E
2
PROM
• Utilizes SDRAMs in TSOPII-54 packages
with registers and PLL.
• Card Size: 133.35 mm
×
38.10 / 43.18 mm
with Gold contact pads and max. 4.00 / 6.80
mm thickness (JEDEC MO-161)
• These modules all fully compatible with the
current industry standard PC133 and PC100
specifications
-7
133
7.5
5.4
133
7.5
5.4
-7.5
133
7.5
5.4
100
10
6
Unit
MHz
ns
ns
MHz
ns
ns
Description
The HYS 72Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs)
organized as 16M
×
72, 32M x 72, 64M
×
72, 128M
×
72 and 256M x 72 high speed memory arrays designed with
Synchronous DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM
and the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive
loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors
are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial
E
2
PROM using the 2-pin I
2
C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second
128 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte
interface in a 133.35 mm long footprint.
INFINEON Technologies
1
2002-07-18
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
Ordering Information
Partnumber
1)
PC133-333:
HYS 72V16300GR-7.5-C
HYS 72V16300GR-7.5-E
HYS 72V16301GR-7.5-C2
HYS 72V32301GR-7.5-C2
HYS 72V32300GR-7.5-C2
HYS 72V32300GR-7.5-D
HYS 72V64300GR-7.5-C2
HYS 72V64300GR-7.5-D
PC133R-333-542-B2 one bank 128 MB Reg. DIMM
PC133R-333-542-B2 one bank 128 MB Reg. DIMM
PC133R-333-542-B2 one bank 256 MB Reg. DIMM
PC133R-333-542-AA one bank 256 MB Reg. DIMM
PC133R-333-542-B2 one bank 512 MB Reg. DIMM
64 MBit (x4)
128 MBit (x8)
128 Mbit (x4)
256 Mbit (x8)
256 MBit (x4)
256 MBit
(x4, stacked)
3)
512 MBit (x4)
512 MBit
(x4, stacked)
3)
Compliance
Code
2)
Description
SDRAM
Technology
HYS 72V128320/1GR-7.5-C2 PC133R-333-542-B2 two banks 1 GByte Reg. DIMM
HYS 72V128320/1GR-7.5-D
HYS 72V128300GR-7.5-A
HYS 72V256320/1GR-7.5-A
PC133R-333-542-B2 one bank 1 GByte Reg. DIMM
PC133R-333-542-B2 two banks 2 GByte Reg. DIMM
PC133-222:
HYS 72V16300GR-7-E
HYS 72V16301GR-7-C2
HYS 72V32301GR-7-C2
HYS 72V32300GR-7-D
HYS 72V64300GR-7-D
HYS 72V128320/1GR-7-D
HYS 72V128300GR-7-A
HYS 72V256320/1GR-7-A
PC133R-222-542-B2 one bank 128 MB Reg. DIMM
PC133R-222-542-B2 one bank 128 MB Reg. DIMM
PC133R-222-542-B2 one bank 256 MB Reg. DIMM
PC133R-222-542-AA one bank 256 MB Reg. DIMM
PC133R-222-542-B2 one bank 512 MB Reg. DIMM
PC133R-222-542-B2 two banks 1 GByte Reg. DIMM
PC133R-222-542-B2 one bank 1 GByte Reg. DIMM
PC133R-222-542-B2 two banks 2 GByte Reg. DIMM
64 MBit (x4)
128 MBit (x8)
128 Mbit (x4)
256 Mbit (x8)
256 MBit (x4)
256 MBit
(x4, stacked)
3)
512 MBit (x4)
512 MBit
(x4, stacked)
3)
Notes:
1.) All part numbers end with a place code, designating the die revision of the components used on the
Registered DIMM module. Consult factory for current revision. Example: HYS 64V32300GR-7.5-D,
indicating Rev.D dies are used for 256Mbit SDRAM components.
2.) The Compliance Code is printed on the modules labels and describes speed sort of the modules,
latencies, access time from clock,SPD revision and Raw Card version acording to the actual JEDEC
standard.
3.) Modules with stacked components are available in two version, with components stacked using a
soldering stacking technique (f.e. HYS72V128320GR-7.5 ) and an welding technique developed by
INFINEON Technologies (f.e. HYS72V128321GR-7.5)
.
INFINEON Technologies
2
2002-07-18
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
Pin Definitions and Functions
A0 - A11, A12
BA0, BA1
DQ0 - DQ63
Address Inputs (A12 is used for
256Mbit based modules only)
Bank Selects
Data Input/Output
DQMB0 - DQMB7
CS0 - CS3
REGE*)
Data Mask
Chip Select
Register Enable
“H” or N.C = registered mode
“L” = buffered mode
Power (+ 3.3 V)
Ground
Clock for Presence Detect
Serial Data Out
No Connection
–
CB0 - CB7
RAS
CAS
WE
CKE0
CLK0 - CLK3
Check Bits
Row Address Strobe
Column Address Strobe
Read/Write Input
Clock Enable
Clock Input
V
DD
V
SS
SCL
SDA
N.C.
–
Note : *) To confirm to this specification, motherboards must pull this pin to high state or no connect.
Address Format
Density Organization Memory SDRAMs
Banks
128 MB 16M
×
72
128 MB 16M
×
72
256 MB 32M x 72
256 MB 32M x 72
512 MB 64M
×
72
1 GB
1 GB
2 GB
128M
×
72
128M
×
72
256M
×
72
1
1
1
1
1
2
1
2
16M
×
4
16M x 8
32M x 4
32M x 8
64M
×
4
64M
×
4
128M
×
4
128M
×
4
# of
# of row/bank/ Refresh Period Interval
SDRAMs columns bits
18
9
18
9
18
36
18
36
12/2/10
12/2/10
12/2/11
13/2/10
13/2/11
13/2/11
13/2/12
13/2/12
4k
4k
4k
8k
8k
8k
8k
8k
64 ms 15.6
µ
s
64 ms 15.6
µ
s
64 ms 15.6
µ
s
64 ms 7.8
µ
s
64 ms 7.8
µ
s
64 ms 7.8
µ
s
64ms
64ms
7.8
µ
s
7.8
µ
s
INFINEON Technologies
3
2002-07-18
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
Pin Configuration
PIN# Symbol
1
V
SS
2
DQ0
3
DQ1
4
DQ2
5
DQ3
6
V
DD
7
DQ4
8
DQ5
9
DQ6
10
DQ7
11
DQ8
V
SS
12
13
DQ9
14
DQ10
15
DQ11
16
DQ12
17
DQ13
18
V
DD
19
DQ14
20
DQ15
21
CB0
22
CB1
23
V
SS
24
N.C.
25
N.C.
26
V
DD
27
WE
28
DQMB0
29
DQMB1
30
CS0
31
DU
32
V
SS
33
A0
34
A2
35
A4
36
A6
37
A8
38
A10 (AP)
39
BA1
V
DD
40
41
V
DD
42
CLK0
PIN#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
Symbol
V
SS
DU
CS2
DQMB2
DQMB3
DU
V
DD
N.C.
N.C.
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
DD
DQ20
N.C.
DU
N.C.
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
N.C.
WP
SDA
SCL
V
DD
PIN#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
Symbol
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
CB4
CB5
V
SS
N.C.
N.C.
V
DD
CAS
DQMB4
DQMB5
CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CLK1
A12
PIN#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Symbol
V
SS
CKE0
CS3
DQMB6
DQMB7
N.C.
V
DD
N.C.
N.C.
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
DD
DQ52
N.C.
DU
REGE
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
N.C.
SA0
SA1
SA2
V
DD
INFINEON Technologies
4
2002-07-18
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
RCS0
RDQMB0
DQ0-DQ3
DQM
CS
DQ0-DQ3
D0
DQM
CS
DQ0-DQ3
D1
DQM
DQ0-DQ3
D2
DQ12-DQ15
CS
DQM
DQ0-DQ3
D3
DQM
CS
DQ0-DQ3
D16
RDQMB4
DQ32-DQ35
DQM
CS
DQ0-DQ3
D8
DQM
CS
DQ0-DQ3
D9
DQM
CS
DQ0-DQ3
D10
CS
DQM
DQ0-DQ3
D11
DQM
CS
DQ0-DQ3
D17
DQ4-DQ7
RDQMB1
DQ8-DQ11
DQ36-DQ39
RDQMB5
DQ40-DQ43
DQ44-DQ47
CB0-CB3
RCS2
RDQMB2
DQ16-DQ19
CB4-CB7
RDQMB6
DQM
CS
DQ0-DQ3
D4
CS
DQM
DQ0-DQ3
D5
CS
DQM
DQ0-DQ3
D6
CS
DQM
DQ0-DQ3
D7
PLL
SDRAMs D0-D17
CLK1, CLK2, CLK3
RCS0/RCS2
RDQMB0-7
RBA0, RBA1
RA0-RA11, RA12
RRAS
RCAS
RCKE0
RWE
12 pF
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
SDRAMs D0-D17
1)
DQ48-DQ51
DQM
CS
DQ0-DQ3
D12
CS
DQM
DQ0-DQ3
D13
CS
DQM
DQ0-DQ3
D14
CS
DQM
DQ0-DQ3
D15
E
2
PROM
(256 word x 8 Bit)
SA0
SA1 SDA
WP
SA2
SCL
DQ20-DQ23
RDQMB3
DQ24-DQ27
DQ52-DQ55
RDQMB7
DQ56-DQ59
DQ28-DQ31
DQ60-DQ63
CLK0
12 pF
CS0/CS2
DQMB0-7
BA0, BA1
A0-A11, A12
RAS
CAS
CKE0
WE
REGE
10 k
Ω
Register
SA0
SA1
SA2
SCL
47 k
Ω
V
CC
C
V
SS
D0-D17, Reg., DLL
D0-D17, Reg., DLL
V
CC
DQ wirding may differ from that decribed
in this drawing; however DQ/DQB relationship
must be maintained as shown
2)
All resistors are 10
Ω
unless otherwise noted
SPB04135
Block Diagram: One Bank 16M x 72, 32M x 72, 64M x 72 and 128M x 72 SDRAM DIMM Modules
HYS72V16300GR, HYS72V32301GR, HYS72V64300GR and HYS72V128320GR
using x4 organized SDRAMs
INFINEON Technologies
5
2002-07-18
嵌入式系统
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