3.3V SDRAM Modules
144 pin SO-DIMM SDRAM Modules
PC100 & PC133
256MB density in COB technique
•
HYS64V32220GCDL
•
•
•
Two bank 32M x 64 non-parity module organisation
suitable for use in PC100 and PC133 applications
Performance:
-7.5
PC133
3-3-3
f
CK
t
AC
Clock frequency (max.)
Clock access time
CAS latency = 2 & 3
133
5.4
-8
PC100
2-2-2
100
6
Units
MHz
ns
•
•
Single +3.3V(± 0.3V ) power supply
Programmable CAS Latency, Burst Length and Wrap Sequence
(Sequential & Interleave)
Auto Refresh (CBR) and Self Refresh
Decoupling capacitors mounted on substrate
All inputs, outputs are LVTTL compatible
Serial Presence Detect with E
2
PROM
Uses COB (“Chip-on-Board”) technique
4096 refresh cycles every 64 ms
Gold contact pad
This module family is fully pin and functional compatible
with the latest INTEL SO-DIMM specification
•
•
•
•
•
•
•
•
Semiconductor Group
1
12.99
7.99
Target Datasheet
144 Pin Eight Byte Small Outline Dual-In-Line Synchronous DRAM Modules
for notebook applications
HYS64V32220GCDL
144 pin SO-DIMM SDRAM Modules
This INFINEON module is an industry standard 144 pin 8-byte Synchronous DRAM (SDRAM) Small
Outline Dual In-line Memory Modules (SO-DIMM) which are organised as 32Mx64 high speed
memory arrays designed for use in non-parity applications. These SO-DIMMs use COB (“Chip-on-
Board”) technology. Decoupling capacitors are mounted on the board.
The DIMMs use optional serial presence detects implemented via a serial E
2
PROM using the two
pin I
2
C protocol. The first 128 bytes are utilized by the DIMM manufacturer and the second 128
bytes are available to the end user.
Product Spectrum:
SDRAMs RowAddr.
Bank
Column Refresh
used
Select
Addr.
16 16Mx8
12
BA0, BA1
10
4k
16 16Mx8
12
BA0, BA1
10
4k
Period
64 ms
64 ms
32M x 64
32M x 64
HYS64V32220GCDL-7.5
HYS64V322220GCDL-8
Note:
All partnumbers end with a place code (not shown), designating the die revision. Consult factory for current
revision. Example: HYS64V32220GCDL-8-C, indicating Rev.C dies are used for SDRAM components.
Card Dimensions:
Organisation
32M x 64
PCB-Board
L-DIM-144-Cx
L x H x T [mm]
67.60 x TBD x 3.80
Pin Names
A0-A11
BA0,BA1
DQ0 - DQ63
RAS
CAS
WE
CKE0
CLK0
DQMB0 - DQMB7
CS0 - CS3
Vcc
Vss
SCL
SDA
N.C.
Address Inputs
Bank Selects
Data Input/Output
Row Address Strobe
Column Address Strobe
Read / Write Input
Clock Enable
Clock Input
Data Mask
Chip Select
Power (+3.3 Volt)
Ground
Clock for Presence Detect
Serial Data Out for Presence Detect
No Connection
Infineon Technologies
2
12.99
Target Datasheet
All INFINEON 144-pin SO-DIMMs provide a high performance, flexible 8-byte interface in a 67,5
mm long footprint.
HYS64V32220GCDL
144 pin SO-DIMM SDRAM Modules
Pin Configuration
PIN #
Front
Side
VSS
DQ0
DQ1
DQ2
DQ3
VCC
DQ4
DQ5
DQ6
DQ7
Vss
DQMB0
DQMB1
Vcc
A0
A1
A2
Vss
DQ8
DQ9
DQ10
DQ11
Vcc
DQ12
DQ13
DQ14
DQ15
Vss
NC
NC
CLK0
Vcc
RAS
WE
CS0
CS1
PIN #
Back
Side
VSS
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
Vss
DQMB4
DQMB5
Vcc
A3
A4
A5
Vss
DQ40
DQ41
DQ42
DQ43
Vcc
DQ44
DQ45
DQ46
DQ47
Vss
NC
NC
CKE0
Vcc
CAS
CKE1
(A12)
(A13)
PIN #
Front
Side
NC
Vss
NC
NC
Vcc
DQ16
DQ17
DQ18
DQ19
Vss
DQ20
DQ21
DQ22
DQ23
Vcc
A6
A8
Vss
A9
A10
Vcc
DQMB2
DQMB3
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
SDA
Vcc
PIN #
Back
Side
CLK1
Vss
NC
NC
Vcc
DQ48
DQ49
DQ50
DQ51
Vss
DQ52
DQ53
DQ54
DQ55
Vcc
A7
BA0
Vss
BA1
A11
Vcc
DQMB6
DQMB7
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
SCL
Vcc
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
Infineon Technologies
3
12.99
Target Datasheet
HYS64V32220GCDL
144 pin SO-DIMM SDRAM Modules
CS1
CS0
CS
DQMB0
DQ(7:0)
DQM
DQ0-DQ7
DQM
DQ0-DQ7
CS
DQMB4
DQ(39:32)
DQM
DQ0-DQ7
CS
DQM
DQ0-DQ7
CS
DQMB1
DQ(15:8)
DQM
DQ0-DQ7
D0
CS
DQM
DQ0-DQ7
D4
CS
DQM
DQ0-DQ7
DQMB5
DQ(47:40)
DQM
DQ0-DQ7
D2
CS
DQM
DQ0-DQ7
D6
CS
DQM
DQ0-DQ7
DQMB2
DQ(23:16)
DQM
DQ0-DQ7
DQMB6
DQ(55:48)
DQM
DQ0-DQ7
DQMB3
DQ(31:24)
DQM
DQ0-DQ7
D1
D0 - D7
DQM
DQ0-DQ7
D5
DQMB7
DQ(63:56)
DQM
DQ0-DQ7
D3
DQM
DQ0-DQ7
D7
A0-A11,BA0,BA1
VDD
VSS
C
E
2
PROM (256wordx8bit)
D0 - D7
D0 - D7
D0 - D15
D0 - D3
D4 - D7
4 SDRAM
4 SDRAM
SA0
SA1
SA2
RAS, CAS, WE
CKE0
CKE1
CLK0
CLK1
SCL
SDA
Note: 1. DQ wiring may differ than describes in this
drawing, however DQ/DQMB/CKE/CS relationship
must be maintained as shown.
2. In this design each of the D0 - D7 components
are represented by two 16M x 8 chips. These two
chips effectively work as a single 16M x 16 device.
Block Diagram for two bank 32M x 64 SDRAM DIMM - Module
Infineon Technologies
4
12.99
Target Datasheet
HYS64V32220GCDL
144 pin SO-DIMM SDRAM Modules
DC Characteristics
T
A
= 0 to 70
°C;
V
SS
= 0 V;
V
DD,
V
DDQ
= 3.3 V
±
0.3 V
Parameter
Input high voltage
Input low voltage
Output high voltage (
I
OUT
= – 4.0 mA)
Output low voltage (
I
OUT
= 4.0 mA)
Input leakage current, any input
(0 V <
V
IN
< 3.6 V, all other inputs = 0 V)
Output leakage current
(DQ is disabled, 0 V <
V
OUT
<
V
CC
)
Symbol
Limit Values
min.
max.
Vcc+0.3
0.8
–
0.4
20
20
V
V
V
V
µA
µA
2.0
– 0.5
2.4
–
– 20
– 20
Unit
V
IH
V
IL
V
OH
V
OL
I
I(L)
I
O(L)
Capacitance
T
A
= 0 to 70
°C;
V
DD
= 3.3 V
±
0.3 V,
f
= 1 MHz
Parameter
Symbol
Limit
Values
16M x 64
max.
Input capacitance
(A0 to A11, BA0, BA1)
Input capacitance
(RAS, CAS, WE)
Input Capacitance
(CLK0, CLK1)
Input capacitance
(CS0, CS1)
Input capacitance
(DQMB0-DQMB7)
Input capacitance
(CKE0, CKE1)
Input / Output capacitance
(DQ0-DQ63)
Input Capacitance
(SCL,SA0-2)
Input/Output Capacitance
Unit
C
I1
C
I2
C
I3
C
I4
C
I5
C
I6
C
IO
C
sc
C
sd
65
75
58
40
15
50
18
8
10
pF
pF
pF
pF
pF
pF
pF
pF
pF
Infineon Technologies
5
12.99
Target Datasheet
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
