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HYMD264646BL8J-J: 产品描述DDR DRAM Module, 64MX64, 0.7ns, CMOS, DIMM-184; 产品类别存储存储; 文件大小221KB，共16页; 制造商SK Hynix(海力士); 官网地址http://www.hynix.com/eng/

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HYMD264646BL8J-J概述

DDR DRAM Module, 64MX64, 0.7ns, CMOS, DIMM-184

HYMD264646BL8J-J规格参数

参数名称	属性值
厂商名称	SK Hynix(海力士)
零件包装代码	DIMM
包装说明	DIMM, DIMM184
针数	184
Reach Compliance Code	compliant
ECCN代码	EAR99
访问模式	FOUR BANK PAGE BURST
最长访问时间	0.7 ns
其他特性	AUTO/SELF REFRESH
最大时钟频率 (fCLK)	166 MHz
I/O 类型	COMMON
JESD-30 代码	R-XDMA-N184
长度	133.35 mm
内存密度	4294967296 bit
内存集成电路类型	DDR DRAM MODULE
内存宽度	64
功能数量	1
端口数量	1
端子数量	184
字数	67108864 words
字数代码	64000000
工作模式	SYNCHRONOUS
最高工作温度	70 °C
最低工作温度
组织	64MX64
输出特性	3-STATE
封装主体材料	UNSPECIFIED
封装代码	DIMM
封装等效代码	DIMM184
封装形状	RECTANGULAR
封装形式	MICROELECTRONIC ASSEMBLY
电源	2.5 V
认证状态	Not Qualified
刷新周期	8192
座面最大高度	4 mm
自我刷新	YES
最大待机电流	0.16 A
最大压摆率	2.64 mA
最大供电电压 (Vsup)	2.7 V
最小供电电压 (Vsup)	2.3 V
标称供电电压 (Vsup)	2.5 V
表面贴装	NO
技术	CMOS
温度等级	COMMERCIAL
端子形式	NO LEAD
端子节距	1.27 mm
端子位置	DUAL
宽度	31.75 mm

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64Mx64 bits

Unbuffered DDR SDRAM DIMM

HYMD264646B(L)8J-J

DESCRIPTION

Hynix HYMD264646B(L)8J-J series is unbuffered 184-pin double data rate Synchronous DRAM Dual In-Line Memory

Modules (DIMMs) which are organized as 64Mx64 high-speed memory arrays. Hynix HYMD264646B(L)8J-J series

consists of sixteen 32Mx8 DDR SDRAM in 400mil TSOPII packages on a184pin glass-epoxy substrate. Hynix

HYMD264646B(L)8J-J series provide a high performance 8-byte interface in 5.25" width form factor of industry stan-

dard. It is suitable for easy interchange and addition.

Hynix HYMD264646B(L)8J-J series is designed for high speed of up to 166MHz and offers fully synchronous opera-

tions referenced to both rising and falling edges of differential clock inputs. While all addresses and control inputs are

latched on the rising edges of the clock, Data, Data strobes and Write data masks inputs are sampled on both rising

and falling edges of it. The data paths are internally pipelined and 2-bit prefetched to achieve very high bandwidth. All

input and output voltage levels are compatible with SSTL_2. High speed frequencies, programmable latencies and

burst lengths allow variety of device operation in high performance memory system.

Hynix HYMD264646B(L)8J-J series incorporates SPD(serial presence detect). Serial presence detect function is

implemented via a serial 2,048-bit EEPROM. The first 128 bytes of serial PD data are programmed by Hynix to identify

DIMM type, capacity and other the information of DIMM and the last 128 bytes are available to the customer.

FEATURES

•

512MB (64M x 64) Unbuffered DDR DIMM based on

32Mx8 DDR SDRAM

JEDEC Standard 184-pin dual in-line memory mod-

ule (DIMM)

2.5V +/- 0.2V VDD and VDDQ Power supply

All inputs and outputs are compatible with SSTL_2

interface

Fully differential clock operations (CK & /CK) with

100MHz/125MHz/133MHz/166MHz

All addresses and control inputs except Data, Data

strobes and Data masks latched on the rising edges

of the clock

Data(DQ), Data strobes and Write masks latched on

both rising and falling edges of the clock

•

Data inputs on DQS centers when write (centered

DQ)

Data strobes synchronized with output data for read

and input data for write

Programmable CAS Latency 2 / 2.5 supported

Programmable Burst Length 2 / 4 / 8 with both

sequential and interleave mode

tRAS Lock-out function supported

Internal four bank operations with single pulsed RAS

Auto refresh and self refresh supported

8192 refresh cycles / 64ms

•

ORDERING INFORMATION

Part No.

HYMD264646B(L)8J-J

Power Supply

=2.5V

DDQ

=2.5V

Clock Frequency

166MHz (*DDR333)

Interface

SSTL_2

Form Factor

184pin Unbuffered DIMM

5.25 x 1.25 x 0.15 inch

* JEDEC Defined Specifications compliant

This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any

responsibility for use of circuits described. No patent licenses are implied.

Rev. 0.2/Dec. 02

HYMD264646BL8J-J

HYMD264646BL8J-J概述

HYMD264646BL8J-J规格参数

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