OMC942723054
HITACHI SINGLE-CHIP MICROCOMPUTER
H8/329 SERIES
H8/329
HD6473298, HD6433298, HD6413298
H8/328
HD6433288
H8/327
HD6473278, HD6433278, HD6413278
H8/326
HD6433268
HARDWARE MANUAL
Preface
The H8/329 Series is a series of high-performance single-chip microcomputers having a fast
H8/300 CPU core and a set of on-chip supporting functions optimized for embedded control.
These include ROM, RAM, two types of timers, a serial communication interface, an A/D
converter, I/O ports, and other functions needed in control system configurations, so that compact,
high-performance systems can be realized easily. The H8/329 Series includes four chips: the
H8/329 with 32K-byte ROM and 1K-byte RAM; the H8/328 with 24K-byte ROM and 1K-byte
RAM; the H8/327 with 16K-byte ROM and 512-byte RAM; and the H8/326 with 8K-byte ROM
and 256-byte RAM.
The H8/329 and H8/327 are available in a masked ROM version, a ZTAT™* (Zero Turn-Around
Time) version, and a ROMless version, providing a quick and flexible response to conditions from
ramp-up through full-scale volume producion, even for applications with frequently-changing
specifications.
This manual describes the hardware of the H8/329 Series. Refer to the
H8/300 Series
Programming Manual
for a detailed description of the instruction set.
Notes: * ZTAT is a registered trademark of Hitachi, Ltd.
Contents
Section 1. Overview
............................................................................................................... 1
1.1
1.2
1.3
Overview...............................................................................................................................
Block Diagram......................................................................................................................
Pin Assignments and Functions............................................................................................
1.3.1 Pin Arrangement......................................................................................................
1.3.2 Pin Functions ...........................................................................................................
1
5
6
6
8
Section 2. MCU Operating Modes and Address Space
................................................ 15
2.1
Overview...............................................................................................................................
2.1.1 Mode Selection ........................................................................................................
2.1.2 Mode and System Control Registers (MDCR and SYSCR) ...................................
System Control Register (SYSCR)—H'FFC4 ......................................................................
Mode Control Register (MDCR)—H'FFC5 .........................................................................
Address Space Maps.............................................................................................................
15
15
16
16
18
19
2.2
2.3
2.4
Section 3. CPU
........................................................................................................................ 23
3.1
3.2
Overview...............................................................................................................................
3.1.1 Features....................................................................................................................
Register Configuration..........................................................................................................
3.2.1 General Registers.....................................................................................................
3.2.2 Control Registers .....................................................................................................
3.2.3 Initial Register Values..............................................................................................
Addressing Modes ................................................................................................................
3.3.1 Addressing Mode.....................................................................................................
3.3.2 How to Calculate Where the Execution Starts ........................................................
Data Formats.........................................................................................................................
3.4.1 Data Formats in General Registers..........................................................................
3.4.2 Memory Data Formats.............................................................................................
Instruction Set .......................................................................................................................
3.5.1 Data Transfer Instructions .......................................................................................
3.5.2 Arithmetic Operations .............................................................................................
3.5.3 Logic Operations .....................................................................................................
3.5.4 Shift Operations.......................................................................................................
3.5.5 Bit Manipulations ....................................................................................................
3.5.6 Branching Instructions.............................................................................................
3.5.7 System Control Instructions ....................................................................................
23
23
24
24
25
26
27
27
29
33
34
35
36
38
40
41
41
43
47
49
3.3
3.4
3.5
i
3.6
3.7
3.5.8 Block Data Transfer Instruction ..............................................................................
CPU States ............................................................................................................................
3.6.1 Program Execution State .........................................................................................
3.6.2 Exception-Handling State........................................................................................
3.6.3 Power-Down State ...................................................................................................
Access Timing and Bus Cycle ..............................................................................................
3.7.1 Access to On-Chip Memory (RAM and ROM) ......................................................
3.7.2 Access to On-Chip Register Field and External Devices ........................................
50
51
52
52
53
53
53
55
Section 4. Exception Handling
............................................................................................ 59
4.1
4.2
Overview...............................................................................................................................
Reset .....................................................................................................................................
4.2.1 Overview .................................................................................................................
4.2.2 Reset Sequence ........................................................................................................
4.2.3 Disabling of Interrupts after Reset...........................................................................
Interrupts...............................................................................................................................
4.3.1 Overview .................................................................................................................
4.3.2 Interrupt-Related Registers......................................................................................
4.3.3 External Interrupts ...................................................................................................
4.3.4 Internal Interrupts ....................................................................................................
4.3.5 Interrupt Handling ...................................................................................................
4.3.6 Interrupt Response Time..........................................................................................
4.3.7 Precaution ................................................................................................................
59
59
59
59
62
62
62
64
66
67
67
72
72
4.3
4.4
Note on Stack Handling........................................................................................................ 73
Section 5. I/O Ports
................................................................................................................ 75
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
Overview............................................................................................................................... 75
Port 1..................................................................................................................................... 77
Port 2..................................................................................................................................... 80
Port 3..................................................................................................................................... 84
Port 4..................................................................................................................................... 88
Port 5..................................................................................................................................... 96
Port 6..................................................................................................................................... 100
Port 7..................................................................................................................................... 111
Section 6. 16-Bit Free-Running Timer
.............................................................................. 113
6.1
Overview............................................................................................................................... 113
6.1.1 Features.................................................................................................................... 113
ii
6.2
6.3
6.4
6.5
6.6
6.7
6.1.2 Block Diagram......................................................................................................... 113
6.1.3 Input and Output Pins .............................................................................................. 115
6.1.4 Register Configuration ............................................................................................ 115
Register Descriptions............................................................................................................ 116
6.2.1 Free-Running Counter (FRC)—H'FF92.................................................................. 116
6.2.2 Output Compare Registers A and B (OCRA and OCRB)—H'FF94....................... 117
6.2.3 Input Capture Registers A to D (ICRA to ICRD)—
H'FF98, H'FF9A, H'FF9C, H'FF9E ......................................................................... 117
6.2.4 Timer Interrupt Enable Register (TIER)—H'FF90 ................................................. 120
6.2.5 Timer Control/Status Register (TCSR)—H'FF91 ................................................... 122
6.2.6 Timer Control Register (TCR)—H'FF96 ................................................................ 125
6.2.7 Timer Output Compare Control Register (TOCR)—H'FF97.................................. 127
CPU Interface ....................................................................................................................... 128
Operation .............................................................................................................................. 130
6.4.1 FRC Incrementation Timing.................................................................................... 130
6.4.2 Output Compare Timing.......................................................................................... 132
6.4.3 Input Capture Timing .............................................................................................. 133
6.4.4 Setting of FRC Overflow Flag (OVF)..................................................................... 136
Interrupts............................................................................................................................... 137
Sample Application............................................................................................................... 137
Application Notes ................................................................................................................. 138
Section 7. 8-Bit Timers
......................................................................................................... 143
7.1
Overview............................................................................................................................... 143
7.1.1 Features.................................................................................................................... 143
7.1.2 Block Diagram......................................................................................................... 143
7.1.3 Input and Output Pins .............................................................................................. 144
7.1.4 Register Configuration ............................................................................................ 145
Register Descriptions............................................................................................................ 145
7.2.1 Timer Counter (TCNT)—H'FFCC (TMR0), H'FFD4 (TMR1)............................... 145
7.2.2 Time Constant Registers A and B (TCORA and TCORB)—
H'FFCA and H'FFCB (TMR0), H'FFD2 and H'FFD3 (TMR1) .............................. 146
7.2.3 Timer Control Register (TCR)—H'FFC8 (TMR0), H'FFD0 (TMR1) .................... 146
7.2.4 Timer Control/Status Register (TCSR)—H'FFC9 (TMR0), H'FFD1 (TMR1) ....... 149
7.2.5 Serial/Timer Control Register (STCR)—H'FFC3 ................................................... 151
Operation .............................................................................................................................. 152
7.3.1 TCNT Incrementation Timing................................................................................. 152
7.3.2 Compare Match Timing........................................................................................... 153
7.2
7.3
iii
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