PRELIMINARY
TECHNOLOGY, INC.
MT9LD272A(X), MT18LD472A(X)
2, 4 MEG x 72 DRAM MODULES
DRAM
MODULE
FEATURES
• Eight CAS#, ECC pinout in a 168-pin, dual-in-line
memory module (DIMM)
• Nonbuffered
• High-performance CMOS silicon-gate process
• Single +3.3V
±0.3V
power supply
• All device pins are TTL-compatible
• Low power, 18mW standby; 3,240mW active, typical
• Refresh modes: RAS#-ONLY, CAS#-BEFORE-RAS#
(CBR), HIDDEN
• 2,048-cycle refresh distributed across 32ms
• FAST PAGE MODE (FPM) or Extended Data-Out
(EDO) PAGE MODE access cycles
• 5V-tolerant inputs and I/Os (5.5V maximum V
IH
level)
• Serial presence-detect (SPD)
2, 4 MEG x 72
16, 32 MEGABYTE, ECC, NONBUFFERED, 3.3V,
8 CAS#, FAST PAGE OR EDO PAGE MODE
PIN ASSIGNMENT (Front View)
168-Pin DIMM
(DE - 16) 2 Meg x 72
(DE - 17) 4 Meg x 72
OPTIONS
• Timing
50ns access
60ns access
70ns access
• Packages
168-pin DIMM (gold)
• Access Cycle
FAST PAGE MODE
EDO PAGE MODE
*EDO version only.
MARKING
-5*
-6
-7
G
Blank
X
KEY TIMING PARAMETERS
EDO Operating Mode
SPEED
-5
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
CAS
90ns
105ns
125ns
50ns
60ns
70ns
25ns
25ns
30ns
25ns
30ns
35ns
15ns
15ns
20ns
10ns
12ns
12ns
FPM Operating Mode
SPEED
-6
-7
t
RC
t
RAC
t
PC
t
AA
t
CAC
t
RP
110ns
130ns
60ns
70ns
35ns
40ns
30ns
35ns
15ns
20ns
40ns
50ns
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
SYMBOL
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
CC
DQ14
DQ15
CB0
CB1
V
SS
NC
NC
V
CC
WE0#
CAS0#
CAS1#
RAS0#
OE0#
V
SS
A0
A2
A4
A6
A8
A10
NC
V
CC
V
CC
RFU
PIN
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
SYMBOL
V
SS
OE2#
RAS2#
CAS2#
CAS3#
WE2#
V
CC
NC
NC
CB2
CB3
V
SS
DQ16
DQ17
DQ18
DQ19
V
CC
DQ20
NC
RFU
NC
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
NC
NC
NC
SDA
SCL
V
CC
PIN
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
SYMBOL
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
CC
DQ46
DQ47
CB4
CB5
V
SS
NC
NC
V
CC
RFU
CAS4#
CAS5#
NC
RFU
V
SS
A1
A3
A5
A7
A9
NC
NC
V
CC
RFU
RFU
PIN
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
SYMBOL
V
SS
RFU
NC
CAS6#
CAS7#
RFU
V
CC
NC
NC
CB6
CB7
V
SS
DQ48
DQ49
DQ50
DQ51
V
CC
DQ52
NC
RFU
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
NC
NC
SA0
SA1
SA2
V
CC
MT9LD272A(X), MT18LD472A(X)
DM60.pm5 – Rev. 6/96
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT9LD272A(X), MT18LD472A(X)
2, 4 MEG x 72 DRAM MODULES
EDO PAGE MODE
EDO PAGE MODE, designated by the “X” version, is an
accelerated FAST PAGE MODE cycle. The primary advan-
tage of EDO is the availability of data-out even after CAS#
goes back HIGH. EDO provides for CAS# precharge time
(
t
CP) to occur without the output data going invalid. This
elimination of CAS# output control provides for pipeline
READs.
FAST-PAGE-MODE modules have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO-PAGE-MODE DRAMs operate similar to FAST-
PAGE-MODE DRAMs, except data will remain valid or
become valid after CAS# goes HIGH during READs, pro-
vided RAS# and OE# are held LOW. If OE# is pulsed while
RAS# and CAS# are LOW, data will toggle from valid data
to High-Z and back to the same valid data. If OE# is toggled
or pulsed after CAS# goes HIGH while RAS# remains
LOW, data will transition to and remain High-Z.
During an application, if the DQ outputs are wire OR’d,
OE# must be used to disable idle banks of DRAMs. Alter-
natively, pulsing WE# to the idle banks during CAS# HIGH
time will also High-Z the outputs. Independent of OE#
control, the outputs will disable after
t
OFF, which is refer-
enced from the rising edge of RAS# or CAS#, whichever
occurs last (reference the MT4LC4M4E8 DRAM data sheet
for additional information on EDO functionality).
PART NUMBERS
EDO Operating Mode
PART NUMBER
DESCRIPTION
MT9LD272AG-xx X
2 Meg x 72 ECC, EDO, 8 CAS#,SPD
MT18LD472AG-xx X
4 Meg x 72 ECC, EDO, 8 CAS#,SPD
xx = speed, SPD = serial presence-detect
FPM Operating Mode
PART NUMBER
DESCRIPTION
MT9LD272AG-xx
2 Meg x 72 ECC, FPM, 8 CAS#,SPD
MT18LD472AG-xx
4 Meg x 72 ECC, FPM, 8 CAS#,SPD
xx = speed, SPD = serial presence-detect
GENERAL DESCRIPTION
The MT9LD272A(X), MT18LD472A(X) are randomly ac-
cessed 16MB and 32MB solid-state memories organized in
a x72 configuration. They are specially processed to operate
from 3.0V to 3.6V for low-voltage memory systems.
During READ or WRITE cycles, each bit is uniquely
addressed through the 21/22 address bits, which are en-
tered 11 bits (A0 -A10) at RAS# time and 10/11 bits (A0-
A10) at CAS# time.
READ and WRITE cycles are selected with the WE#
input. A logic HIGH on WE# dictates READ mode while a
logic LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last. An EARLY WRITE occurs
when WE# is taken LOW prior to CAS# falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE# falls
after CAS# was taken LOW. During EARLY WRITE cycles,
the data-outputs (Q) will remain High-Z regardless of the
state of OE#. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE# must be taken HIGH to disable the
data-outputs prior to applying input data. If a LATE WRITE
or READ-MODIFY-WRITE is attempted while keeping
OE# LOW, no write will occur, and the data-outputs will
drive read data from the accessed location.
REFRESH
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
Also, the chip is preconditioned for the next cycle during
the RAS# HIGH time. Correct memory cell data is pre-
served by maintaining power and executing any RAS#
cycle (READ, WRITE) or RAS# refresh cycle (RAS#-ONLY,
CBR or HIDDEN) so that all combinations of RAS# ad-
dresses (A0-A9/A10) are executed at least every
t
REF,
regardless of sequence. The CBR REFRESH cycle will in-
voke the internal refresh counter for automatic RAS# ad-
dressing.
FAST PAGE MODE
FAST PAGE MODE operations allow faster data opera-
tions (READ or WRITE) within a row-address-defined
page boundary. The FAST PAGE MODE cycle is always
initiated with a row-address strobed-in by RAS# followed
by a column-address strobed-in by CAS#. CAS# may be
toggled-in by holding RAS# LOW and strobing-in different
column-addresses, thus executing faster memory cycles.
Returning RAS# HIGH terminates the FAST PAGE MODE
operation.
SERIAL PRESENCE-DETECT
This module incorporates Serial Presence-Detect (SPD).
The SPD function is implemented using a 2,028 bit EEPROM.
This nonvolatile storage device contains data programmed
by Micron that identifies the module type and various
DRAM organization and timing parameters. System READ/
WRITE operations to the EEPROM device occur via a
standard IIC bus using the DIMM’s SCL (clock) and SDA
(data) signals, together with SA(2:0) which provide the
EEPROM device address. The EEPROM device operates
with a V
CC
of 3.3V
±0.3V.
MT9LD272A(X), MT18LD472A(X)
DM60.pm5 – Rev. 6/96
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
PRELIMINARY
TECHNOLOGY, INC.
MT9LD272A(X), MT18LD472A(X)
2, 4 MEG x 72 DRAM MODULES
PIN DESCRIPTIONS
PIN NUMBERS
30, 45
SYMBOL
RAS0#, RAS2#
TYPE
Input
DESCRIPTION
Row-Address Strobe: RAS# is used to clock-in the 11
row-address bits. Two RAS# inputs allow for one x72
bank or two x36 banks.
Column-Address Strobe: CAS# is used to clock-in the 11
column-address bits, enable the DRAM output buffers
and strobe the data inputs on WRITE cycles.
Write Enable: WE# is the READ/WRITE control for the
DQ pins. If WE# is LOW prior to CAS# going LOW, the
access is an EARLY WRITE cycle. If WE# is HIGH while
CAS# is LOW, the access is a READ cycle, provided OE#
is also LOW. If WE# goes LOW after CAS# goes LOW,
then the cycle is a LATE WRITE cycle. A LATE WRITE
cycle is generally used in conjunction with a READ cycle
to form a READ-MODIFY-WRITE cycle.
Output Enable: OE# is the input/output control for the DQ
pins. These signals may be driven, allowing LATE WRITE
cycles.
Address Inputs: These inputs are multiplexed and clocked
by RAS# and CAS#.
Data I/O: For WRITE cycles, DQ0-DQ63 act as inputs to
the addressed DRAM location. For READ access cycles,
DQ0-DQ63 act as outputs for the addressed DRAM
location.
28, 29, 46, 47, 112,
113, 130, 131
27, 48
CAS0#-CAS7#
Input
WE0#, WE2#
Input
31, 44
OE0#, OE2#
Input
33-38, 117-121
2-5, 7-11, 13-17, 19-20,
55-58, 60, 65-67, 69-72,
74-77, 86-89,91-95,
97-101, 103-104,
139-142, 144, 149-151,
153-156, 158-161
21-22, 52-53, 105-106,
136-137
42, 62, 111, 115,
125-126, 128, 132, 146
6, 18, 26, 40, 41, 49, 59,
73, 133, 143, 157, 168
1, 12, 23, 32, 43, 54, 64,
68, 78, 85, 96, 107, 116,
127, 138, 148, 152, 162
82
A0-A10
DQ0-DQ63
Input
Input/
Output
CB0-CB7
RFU
V
CC
V
SS
Input/Output
—
Supply
Supply
Check Bits.
RFU: These pins should be left unconnected
(reserved for future use).
Power Supply: +3.3V
±0.3V.
Ground
SDA
Input/Output
Serial Presence-Detect Data. SDA is a bidirectional pin
used to transfer addresses and data into and data out of
the presence-detect portion of the module.
Serial Clock for Presence-Detect. SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs. These pins are used to
configure the presence-detect device.
83
SCL
Input
165-167
SA0-SA2
Input
MT9LD272A(X), MT18LD472A(X)
DM60.pm5 – Rev. 6/96
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©1996,
Micron Technology, Inc.
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