KM68V1000E, KM68U1000E Family
Document Title
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
Preliminary
CMOS SRAM
Revision History
Revision No.
0.0
History
Design target
Draft Data
September 9, 1998
Remark
Preliminary
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.
1
Revision 0.0
September 1998
KM68V1000E, KM68U1000E Family
128Kx8 bit Low Power and Low Voltage CMOS Static RAM
FEATURES
•
Process Technology : TFT
•
Organization : 128Kx8
•
Power Supply Voltage
KM68V1000E Family : 3.0V ~ 3.6V
KM68U1000E Family : 2.7V ~ 3.3V
•
Low Data Retention Voltage : 2V(Min)
•
Three state output and TTL Compatible
•
Package Type : 32-SOP-525,
32-TSOP1-0820F, 32-TSOP1-0813.4F
Preliminary
CMOS SRAM
GENERAL DESCRIPTION
The KM68V1000E and KM68U1000E families are fabricated
by SAMSUNG′s advanced CMOS process technology. The
families support various operating temperature ranges and
have various package types for user flexibility of system
design. The families also support low data retention voltage
for battery back-up operation with low data retention current.
PRODUCT FAMILY
Power Dissipation
Product Family
KM68V1000EL-L
KM68U1000EL-L
KM68V1000ELI-L
KM68U1000ELI-L
1. The parameters are tested with 30pF test load
Operating Temperature
Vcc Range
3.0~3.6V
2.7~3.3V
Speed(ns)
Standby
(I
SB1
, Max)
Operating
(I
CC2,
Max)
PKG Type
Commercial(0~70°C)
70
1)
/100
10µA
30mA
Industrial(-40~85°C)
3.0~3.6V
2.7~3.3V
32-SOP
32-TSOP1-0820F
32-TSOP1-0813.4F
PIN DESCRIPTION
N.C
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
VCC
A15
CS2
A11
A9
A13 A8
A13
A8
WE
CS2
A9
A15
A11 VCC
OE NC
A16
A10 A14
A12
CS1 A7
I/O8 A6
A5
I/O7 A4
WE
I/O6
I/O5
I/O4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3
FUNCTIONAL BLOCK DIAGRAM
Clk gen.
Precharge circuit.
32-SOP
25
24
23
22
21
20
19
18
17
32-TSOP
32-
S
TSOP
Type1-Forward
Row
select
Memory array
1024 rows
128×8 columns
I/O
1
I/O
8
Data
cont
I/O Circuit
Column select
Name
A
0
~A
16
WE
CS
1
,CS
2
OE
I/O
1
~I/O
8
Vcc
Vss
N.C.
Function
Address Inputs
Write Enable Input
Chip Select Input
Output Enable Input
Data Inputs/Outputs
Power
Ground
No Connection
CS
1
CS
2
WE
OE
Data
cont
Control
logic
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to change products and specifications without notice.
2
Revision 0.0
September 1998
KM68V1000E, KM68U1000E Family
PRODUCT LIST
Commercial Temperature Products(0~70°C)
Part Name
KM68V1000ELG-7L
KM68V1000ELG-10L
KM68V1000ELT-7L
KM68V1000ELT-10L
KM68V1000ELTG-7L
KM68V1000ELTG-10L
KM68U1000ELG-7L
KM68U1000ELG-10L
KM68U1000ELT-7L
KM68U1000ELT-10L
KM68U1000ELTG-7L
KM68U1000ELTG-10L
Preliminary
CMOS SRAM
Industrial Temperature Products(-40~85°C)
Part Name
KM68V1000ELGI-7L
KM68V1000ELGI-10L
KM68V1000ELTI-7L
KM68V1000ELTI-10L
KM68V1000ELTGI-7L
KM68V1000ELTGI-10L
KM68U1000ELGI-7L
KM68U1000ELGI-10L
KM68U1000ELTI-7L
KM68U1000ELTI-10L
KM68U1000ELTGI-7L
KM68U1000ELTGI-10L
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-SOP, 70ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 70ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-sTSOP F, 70ns, 3.0V
32-sTSOP F, 100ns, 3.0V
Function
32-SOP, 70ns, 3.3V
32-SOP, 100ns, 3.3V
32-TSOP F, 70ns, 3.3V
32-TSOP F, 100ns, 3.3V
32-sTSOP F, 70ns, 3.3V
32-sTSOP F, 100ns, 3.3V
32-SOP, 70ns, 3.0V
32-SOP, 100ns, 3.0V
32-TSOP F, 70ns, 3.0V
32-TSOP F, 100ns, 3.0V
32-sTSOP F, 70ns, 3.0V
32-sTSOP F, 100ns, 3.0V
FUNCTIONAL DESCRIPTION
CS
1
H
X
1)
L
L
L
CS
2
X
1)
L
H
H
H
OE
X
1)
X
1)
H
L
X
1)
WE
X
1)
X
1)
H
H
L
I/O
High-Z
High-Z
High-Z
Dout
Din
Mode
Deselected
Deselected
Output Disabled
Read
Write
Power
Standby
Standby
Active
Active
Active
1. X means don′t care (Must be in high or low states)
ABSOLUTE MAXIMUM RATINGS
1)
Item
Voltage on any pin relative to Vss
Voltage on Vcc supply relative to Vss
Power Dissipation
Storage temperature
Operating Temperature
Symbol
V
IN
,V
OUT
V
CC
P
D
T
STG
T
A
-40 to 85
Ratings
-0.5 to V
CC
+0.5
-0.3 to 4.6
1.0
-65 to 150
0 to 70
Unit
V
V
W
°C
°C
°C
Remark
-
-
-
-
KM68V1000EL, KM68U1000EL
KM68V1000ELI, KM68U1000ELI
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
Revision 0.0
September 1998
KM68V1000E, KM68U1000E Family
RECOMMENDED DC OPERATING CONDITIONS
1)
Item
Supply voltage
Ground
Input high voltage
Input low voltage
Symbol
Vcc
Vss
V
IH
V
IL
Product
KM68V1000E Family
KM68U1000E Family
All Family
KM68V1000E, KM68U1000E Family
KM68V1000E, KM68U1000E Family
Min
3.0
2.7
0
2.2
-0.3
3)
Preliminary
CMOS SRAM
Typ
3.3
3.0
0
-
-
Max
3.6
3.3
0
Vcc+0.3
0.6
Unit
V
V
V
V
Note:
1. Commercial Product : T
A
=0 to 70°C, otherwise specified
Industrial Product : T
A
=-40 to 85°C, otherwise specified
2. Overshoot : Vcc+2.0V in case of pulse width≤30ns
3. Undershoot : -2.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested.
CAPACITANCE
1
)
(f=1MHz, TA=25°C)
Item
Input capacitance
Input/Output capacitance
1. Capacitance is sampled, not 100% tested
Symbol
C
IN
C
IO
Test Condition
V
IN
=0V
V
IO
=0V
Min
-
-
Max
8
10
Unit
pF
pF
DC AND OPERATING CHARACTERISTICS
Item
Input leakage current
Output leakage current
Operating power supply current
Average operating current
Output low voltage
Output high voltage
Standby Current(TTL)
Standby Current(CMOS)
Symbol
I
LI
I
LO
I
CC
I
CC1
I
CC2
V
OL
V
OH
I
SB
I
SB1
V
IN
=Vss to Vcc
CS
1
=V
IH
or CS
2
=V
IL
or OE=V
IH
or WE=V
IL
, V
IO
=Vss to Vcc
I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
, Read
Cycle time=1µs, 100%duty, I
IO
=0mA, CS
1
≤0.2V,
CS
2
≥Vcc-0.2V,
V
IN
≤0.2V
Cycle time=Min, 100% duty, I
IO
=0mA, CS
1
=V
IL
, CS
2
=V
IH,
V
IN
=V
IH
or V
IL
Test Conditions
Min Typ Max Unit
-1
-1
-
-
-
-
2.4
-
-
-
-
-
-
25
-
-
-
0.2
1
1
4
3
30
0.4
-
0.3
10
µA
µA
mA
mA
mA
V
V
mA
µA
I
OL
=2.1mA
I
OH
=-1.0mA
CS
1
=V
IH
, CS2=V
IL
, Other inputs=V
IH
or V
IL
CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V,
Other inputs=0~Vcc
4
Revision 0.0
September 1998
KM68V1000E, KM68U1000E Family
AC OPERATING CONDITIONS
TEST CONDITIONS
( Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V
Input rising and falling time : 5ns
Input and output reference voltage :1.5V
Output load(see right) : C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
Preliminary
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
(KM68V1000E Family : V
CC
=3.0~3.6V, KM68U1000E Family : V
CC
=2.7~3.3V
Commercial Product : T
A
=0 to 70°C, Industrial Product : T
A
=-40 to 85°C
)
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1
, t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR
t
WHZ
t
DW
t
DH
t
OW
70
-
-
-
10
5
0
0
10
70
60
0
60
55
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
100ns
Min
100
-
-
-
10
5
0
0
15
100
80
0
80
70
0
0
40
0
5
Max
-
100
100
50
-
-
30
30
-
-
-
-
-
-
-
30
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Data retention current
Data retention set-up time
Recovery time
Symbol
V
DR
I
DR
t
SDR
t
RDR
CS
1
≥Vcc-0.2V
1)
Vcc=3.0V, CS
1
≥Vcc-0.2V
1)
See data retention waveform
Test Condition
Min
2.0
-
0
5
Typ
-
0.2
-
-
Max
3.6
10
-
-
Unit
V
µA
ms
1. CS
1
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V(CS
1
controlled) or CS
2
≤0.2V(CS
2
controlled)
5
Revision 0.0
September 1998
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