NJU3610
1bit Delta-Sigma Stereo ADC
General Description
The NJU3610 is the stereo Analog to Digital Convector (ADC) that covers from 8
to 192 kHz sampling frequency. The NJU3610 provides 1bit Delta-Sigma
technology with high accuracy and low power consumption. The analog inputs are
differential signal and stereo 4-1 selectors are provided. The NJU3610 provides two
power-supply 1.8V / 3.3V(typical) or single power-supply 3.3V(typical) application.
Package
Features
NJU3610FR3
1bit Delta-Sigma stereo ADC
64fs over sampling (MCK=256fs, 384fs)
32fs over sampling (MCK=128fs)
Digital Filter
High-pass filter
Stereo 4-1 selectors
Sampling Rate
: 8 to 192kHz
Dynamic Range
: 100dB(typ@3.3V, 96kHz)
S/N
: 100dB(typ@3.3V, 96kHz)
S/(N+D)
: 90dB(typ@3.3V, 48kHz, -1.0dBFS)
Master Clock
: 128fs(8 to 192kHz), 256fs / 384fs(8 to 96kHz)
Power Supply
: Single power supply 3.0 to 3.6V(3.3Vtyp) Built-in regulator using together
: Two power supply 3.0 to 3.6V(Analog, I/O:3.3Vtyp)
1.65 to 2.0V(Digital:1.8Vtyp)
Digital Audio Format
: 24/16bit Left-justified, I
2
S Master/Slave
Operating Temperature
: -40 to +85°C
Package
: LQFP48-R3 (Pb-Free)
Ver.2009.12.4
-1-
NJU3610
Pin Description
Table.1 Pin Description
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Symbol
AINLP3
AINLN3
AINLP2
AINLN2
AINLP1
AINLN1
AVSS
AVDD
VDD33
VSS
VREGI
VREGO
SDO
LRCK
BCK
HPF
VSS
VDD18
VDD33
MCK
FMT0
FMT1
SEL0
SEL1
PDNb
RESETb
MODE0
MODE1
AVDD
AVSS
AINRN1
AINRP1
AINRN2
AINRP2
AINRN3
AINRP3
AINRN4
AINRP4
REFRP
REFRN
VCOM
AVDD
AVSS
TEST
REFLN
REFLP
AINLP4
AINLN4
I/O
AI
AI
AI
AI
AI
AI
AG
AP
DP
DG
RI
RO
DO
DIO
DIO
DI
DG
DL
DP
DI
DI
DI
DI
DI
DI
DI
DI
DI
AP
AG
AI
AI
AI
AI
AI
AI
AI
AI
AI
AI
AO
AP
AG
AI
AI
AI
AI
AI
Description
Lch Analog Positive Input 3 Pin
Lch Analog Negative Input 3 Pin
Lch Analog Positive Input 2 Pin
Lch Analog Negative Input 2 Pin
Lch Analog Positive Input 1 Pin
Lch Analog Negative Input 1 Pin
Analog Ground Pin
Analog Power Supply Pin, 3.3V
Digital Power Supply Pin, 3.3V
Digital Ground Pin
Built-in Regulator Input Pin, 3.3V
Built-in Regulator Output Pin, 1.8V (typ)
Audio Serial Data Output Pin
LR Clock
Bit Clock
HPF for Off-set Cancel (“H”: ON, “L”: OFF)
Digital Ground Pin
Digital Power Supply Pin, 1.8V
Digital Power Supply Pin, 3.3V
Master Clock Input Pin
Control Serial Data Format 0 Pin
Control Serial Data Format 1 Pin
Control Input Selector 0 Pin
Control Input Selector 1 Pin
Power Down Mode Pin (”H”: Power up, “L”: Power down)
Reset Pin (“H”: Reset OFF, “L”: Reset ON)
Control Mode 0 Pin
Control Mode 1 Pin
Analog Power Supply Pin, 3.3V
Analog Ground Pin
Rch Analog Negative Input 1 Pin
Rch Analog Positive Input 1 Pin
Rch Analog Negative Input 2 Pin
Rch Analog Positive Input 2 Pin
Rch Analog Negative Input 3 Pin
Rch Analog Positive Input 3 Pin
Rch Analog Negative Input 4 Pin
Rch Analog Positive Input 4 Pin
Rch Voltage Reference Input Pin, AVDD
Rch Voltage Reference Input Pin, GND
Common Voltage Output Pin, AVDD/2
Connected to AVSS with a 10uF electrolytic capacitor.
Analog Power Supply Pin, 3.3V
Analog Ground Pin
Test Pin (Connected to AVSS)
Lch Voltage Reference Input Pin, GND
Lch Voltage Reference Input Pin, AVDD
Lch Analog Positive Input 4 Pin
Lch Analog Negative Input 4 Pin
* AP : Analog power supply, 3.3V
AO : Analog output
DL : Digital power supply, 1.8V
RI : built-in regulator input
DI : Digital input
DIO : Bi-directional of Digital
AG : Analog ground AI : Analog input
DP : Digital power supply, 3.3V
DG : Digital ground and built-in regulator ground
RO : built-in regulator output
DO : Digital output
-4-
Ver. 2009.12.4
NJU3610
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings
Parameter
Analog
Digital
Power supplies
Built-in Regulator
Input
Built-in Regulator
Output
Digital Input
Pin Voltage
Digital Output
Analog Input
VCOM Output
Power Dissipation
Operating Temperature
Storage Temperature
* AVDD
* VDD33
* VDD18
* VREGI
* VREGO
* V
X(IN)
* V
X(OUT)
* V
X(AIN)
* V
X(VCOM)
Note 1)
Symbol
AVDD
VDD33
VDD18
VREGI
VREGO
V
x(IN)
V
x(OUT)
V
x(AIN)
V
x(VCOM)
P
D
T
OPR
T
STR
800
Mounted on two-layer board of based on the JEDEC.
(VSS=AVSS=0V=GND, Ta=25°C)
Rating
-0.3 to +4.2
-0.3 to +2.3
-0.3 to +4.2
-0.3 to +2.3
-0.3 to +5.5 (VDD33
≥
3.0V)
-0.3 to +4.2 (VDD33<3.0V)
-0.3 to VDD33 + 0.3
-0.3 to AVDD + 0.3
mW
°C
°C
V
Units
-40 to +85
-40 to +125
: 8, 29, 42pin
: 9pin
: 18pin
: 11pin
: 12pin
: 16, 20-28pin, and 14-15pin (set in the state of the input.)
: 13pin, and 14-15pin (set in the state of the output.)
: 1-6, 31-40, 44-48pin
: 41pin
Note 2)
If the LSI is used on condition beyond the absolute maximum rating, the LSI may be destroyed. Using
LSI within electrical characteristics is strongly recommended for normal operation. Use beyond the
electrical characteristics conditions will cause malfunction and poor reliability.
Please do not open the digital input terminal. Moreover, please do not open the digital I/O terminal set
in the state of the input.
Recommended operating conditions
Table 3. Recommended operating conditions
Parameter
Analog
Power
Supplies
Digital
Built-in Regulator Input
Symbol
AVDD
*1
VDD33
*1
VDD18
*2
VREGI
*3
Recommended operating
conditions
3.0 to 3.6
AVDD33
≥
VDD33
1.65 to 2.0
(Or, a built-in regulator supplies
the voltage.)
3.0 to VDD33
Units
V
*1 VDD33 is recommended to be turned on from AVDD and simultaneous or AVDD back.
*2 The power up sequence VDD18 is not critical.
*3 When a built-in regulator is used, VREGI is connected with VDD33. When a built-in regulator is not used,
VREGI and VREGO are connected with VSS.
Ver.2009.12.4
-5-
微控制器 MCU
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