SN54ACT00, SN74ACT00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS523D − AUGUST 1995 − REVISED OCTOBER 2003
D
4.5-V to 5.5-V V
CC
Operation
D
Inputs Accept Voltages to 5.5 V
SN54ACT00 . . . J OR W PACKAGE
SN74ACT00 . . . D, DB, N, NS, OR PW PACKAGE
(TOP VIEW)
D
Max t
pd
of 8 ns at 5 V
D
Inputs Are TTL-Voltage Compatible
SN54ACT00 . . . FK PACKAGE
(TOP VIEW)
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1B
1A
NC
V
CC
4B
4A
NC
4Y
NC
3B
NC − No internal connection
ORDERABLE
PART NUMBER
SN74ACT00N
SN74ACT00D
SN74ACT00DR
SN74ACT00NSR
SN74ACT00DBR
SN74ACT00PW
SN74ACT00PWR
SNJ54ACT00J
SNJ54ACT00W
AD00
SNJ54ACT00J
SNJ54ACT00W
ACT00
ACT00
AD00
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tube
Tube
FUNCTION TABLE
(each gate)
B
H
X
L
OUTPUT
Y
L
H
H
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
description/ordering information
The ‘ACT00 devices contain four independent 2-input NAND gates. Each gate performs the Boolean function
of Y = A
S
B or Y = A + B in positive logic.
ORDERING INFORMATION
TA
PDIP − N
SOIC − D
−40°C to 85 C
−40 C 85°C
SOP − NS
SSOP − DB
TSSOP − PW
CDIP − J
−55°C to 125 C
−55 C 125°C
CFP − W
PACKAGE†
TOP-SIDE
MARKING
SN74ACT00N
LCCC − FK
Tube
SNJ54ACT00FK
SNJ54ACT00FK
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
INPUTS
A
H
L
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
2003, Texas Instruments Incorporated
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
2Y
GND
NC
3Y
3A
1
SN54ACT00, SN74ACT00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS523D − AUGUST 1995 − REVISED OCTOBER 2003
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
Input voltage range, V
I
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Output voltage range, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
CC
+ 0.5 V
Input clamp current, I
IK
(V
I
< 0 or V
I
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Output clamp current, I
OK
(V
O
< 0 or V
O
> V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±20
mA
Continuous output current, I
O
(V
O
= 0 to V
CC
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±50
mA
Continuous current through V
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
±200
mA
Package thermal impedance,
θ
JA
(see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
stg
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 3)
SN54ACT00
MIN
VCC
VIH
VIL
VI
VO
IOH
IOL
∆t/∆v
Supply voltage
High-level input voltage
Low-level input voltage
Input voltage
Output voltage
High-level output current
Low-level output current
Input transition rise or fall rate
0
0
4.5
2
0.8
VCC
VCC
−24
24
8
0
0
MAX
5.5
SN74ACT00
MIN
4.5
2
0.8
VCC
VCC
−24
24
8
MAX
5.5
UNIT
V
V
V
V
V
mA
mA
ns/V
TA
Operating free-air temperature
−55
125
−40
85
°C
NOTE 3: All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs,
literature number SCBA004.
2
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
SN54ACT00, SN74ACT00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS523D − AUGUST 1995 − REVISED OCTOBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
IOH = −50
µA
A
VOH
IOH = −24 mA
IOH = −50 mA†
IOH = −75 mA†
IOL = 50
µA
A
VOL
IOL = 24 mA
IOL = 50 mA†
IOL = 75 mA†
II
ICC
∆I
CC‡
Ci
VI = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
Other inputs at GND or VCC
IO = 0
VCC
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
5.5 V
0.6
±0.1
2
±1
40
1.6
0.001
0.001
0.1
0.1
0.36
0.36
0.1
0.1
0.5
0.5
1.65
1.65
±1
20
1.5
µA
µA
mA
pF
TA = 25°C
MIN
TYP
MAX
4.4
5.4
3.86
4.86
4.49
5.49
SN54ACT00
MIN
4.4
5.4
3.7
4.7
3.85
3.85
0.1
0.1
0.44
0.44
V
MAX
SN74ACT00
MIN
4.4
5.4
3.76
4.76
V
MAX
UNIT
VI = VCC or GND
5V
2.6
† Not more than one output should be tested at a time, and the duration of the test should not exceed 2 ms.
‡ This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or VCC.
switching characteristics over recommended operating free-air temperature range,
V
CC
= 5 V
±
0.5 V (unless otherwise noted) (see Figure 1)
PARAMETER
tPLH
tPHL
FROM
(INPUT)
A or B
TO
(OUTPUT)
Y
TA = 25°C
MIN
TYP
MAX
1.5
1.5
5.5
4
9
7
SN54ACT00
MIN
1
1
MAX
9.5
8
SN74ACT00
MIN
1
1
MAX
9.5
8
UNIT
ns
operating characteristics, V
CC
= 5 V, T
A
= 25°C
PARAMETER
Cpd
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF,
f = 1 MHz
TYP
40
UNIT
pF
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
3
SN54ACT00, SN74ACT00
QUADRUPLE 2 INPUT POSITIVE NAND GATES
SCAS523D − AUGUST 1995 − REVISED OCTOBER 2003
PARAMETER MEASUREMENT INFORMATION
TEST
tPLH/tPHL
S1
Open
Input
tPLH
2
×
VCC
From Output
Under Test
CL = 50 pF
(see Note A)
500
Ω
S1
Open
In-Phase
Output
tPHL
Out-of-Phase
Output
LOAD CIRCUIT
50% VCC
50% VCC
3V
1.5 V
1.5 V
0V
tPHL
VOH
50% VCC
VOL
tPLH
VOH
50% VCC
VOL
500
Ω
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR
≤
1 MHz, ZO = 50
Ω,
tr
≤
2.5 ns, tf
≤
2.5 ns.
C. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303
•
DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
5962-8769901M2A
Status
(1)
Package Type Package Pins Package
Drawing
Qty
LCCC
FK
20
1
Eco Plan
(2)
Lead/Ball Finish
POST-PLATE
MSL Peak Temp
(3)
Op Temp (°C)
-55 to 125
Device Marking
(4/5)
Samples
ACTIVE
TBD
N / A for Pkg Type
5962-
8769901M2A
SNJ54
ACT00FK
5962-8769901MC
A
SNJ54ACT00J
5962-8769901MD
A
SNJ54ACT00W
ACT00
5962-8769901MCA
ACTIVE
CDIP
J
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8769901MDA
ACTIVE
CFP
W
14
1
TBD
A42
N / A for Pkg Type
-55 to 125
SN74ACT00D
SN74ACT00DBLE
SN74ACT00DBR
SN74ACT00DBRE4
SN74ACT00DBRG4
SN74ACT00DE4
SN74ACT00DG4
SN74ACT00DR
SN74ACT00DRE4
SN74ACT00DRG4
SN74ACT00N
SN74ACT00NE4
SN74ACT00NSR
ACTIVE
OBSOLETE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SSOP
SSOP
SSOP
SSOP
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SO
D
DB
DB
DB
DB
D
D
D
D
D
N
N
NS
14
14
14
14
14
14
14
14
14
14
14
14
14
50
Green (RoHS
& no Sb/Br)
TBD
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
Pb-Free
(RoHS)
Green (RoHS
& no Sb/Br)
CU NIPDAU
Call TI
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2000
2000
2000
50
50
2500
2500
2500
25
25
2000
AD00
AD00
AD00
ACT00
ACT00
ACT00
ACT00
ACT00
SN74ACT00N
SN74ACT00N
ACT00
Addendum-Page 1
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
