Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
FEATURES
•
Cascadable
•
Synchronous or asynchronous preset
•
Output capability: standard
•
I
CC
category: MSI
GENERAL DESCRIPTION
The 74HC/HCT40102 are high-speed Si-gate CMOS
devices and are pin compatible with the “40102” of the
“4000B” series. They are specified in compliance with
JEDEC standard no. 7A.
The 74HC/HCT40102 consist each of an 8-bit
synchronous down counter with a single output which is
active when the internal count is zero. The “40102” is
configured as two cascaded 4-bit BCD counters and has
control inputs for enabling or disabling the clock (CP), for
clearing the counter to its maximum count, and for
presetting the counter either synchronously or
asynchronously. All control inputs and the terminal count
output (TC) are active-LOW logic.
In normal operation, the counter is decremented by one
count on each positive-going transition of the clock (CP).
Counting is inhibited when the terminal enable input (TE)
is HIGH. The terminal count output (TC) goes LOW when
the count reaches zero if TE is LOW, and remains LOW for
one full clock period.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°C;
t
r
= t
f
= 6 ns
74HC/HCT40102
When the synchronous preset enable input (PE) is LOW,
data at the jam input (P
0
to P
7
) is clocked into the counter
on the next positive-going clock transition regardless of the
state of TE. When the asynchronous preset enable input
(PL) is LOW, data at the jam input (P
0
to P
7
) is
asynchronously forced into the counter regardless of the
state of PE, TE, or CP. The jam inputs (P
0
to P
7
) represent
two 4-bit BCD words.
When the master reset input (MR) is LOW, the counter is
asynchronously cleared to its maximum count (decimal
99) regardless of the state of any other input. The
precedence relationship between control inputs is
indicated in the function table.
If all control inputs except TE are HIGH at the time of zero
count, the counters will jump to the maximum count, giving
a counting sequence of 100 clock pulses long.
The “40102” may be cascaded using the TE input and the
TC output, in either a synchronous or ripple mode.
APPLICATIONS
•
Divide-by-n counters
•
Programmable timers
•
Interrupt timers
•
Cycle/program counters
TYPICAL
SYMBOL
t
PHL
/ t
PLH
f
max
C
I
C
PD
Notes
1. C
PD
is used to determine the dynamic power dissipation (P
D
in
µW):
P
D
= C
PD
×
V
CC2
×
f
i
+ ∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz
f
o
= output frequency in MHz
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs
C
L
= output load capacitance in pF
V
CC
= supply voltage in V
PARAMETER
propagation delay CP to TC
maximum clock frequency
input capacitance
power dissipation capacitance per package
notes 1 and 2
CONDITIONS
HC
C
L
= 15 pF; V
CC
= 5 V
30
30
3.5
20
HCT
31
30
3.5
25
ns
MHz
pF
pF
UNIT
December 1990
2
Philips Semiconductors
Product specification
8-bit synchronous BCD down counter
2. For HC the condition is V
I
= GND to V
CC
For HCT the condition is V
I
= GND to V
CC
−
1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”.
PIN DESCRIPTION
PIN NO.
1
2
3
4, 5, 6, 7, 10, 11, 12, 13
8
9
14
15
16
SYMBOL
CP
MR
TE
P
0
to P
7
GND
PL
TC
PE
V
CC
NAME AND FUNCTION
74HC/HCT40102
clock input (LOW-to-HIGH, edge-triggered)
asynchronous master reset input (active LOW)
terminal enable input
jam inputs
ground (0 V)
asynchronous preset enable input (active LOW)
terminal count output (active LOW)
synchronous preset enable input (active LOW)
positive supply voltage
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
December 1990
3
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