ADVANCE
8, 16 MEG x 72
DDR SDRAM DIMMs
DDR SDRAM
DIMM MODULE
FEATURES
• 184-pin dual in-line memory module (DIMM)
• Utilizes 100 MHz and 133 MHz DDR SDRAM
components
• ECC-optimized pinout
• 64MB (8 Meg x 72), 128MB (16 Meg x 72)
• V
DD
= +2.5V ±0.2V, V
DD
Q = +2.5V ±0.2V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data, i.e., source-synchronous data
capture
• Differential clock inputs (CK0 and CK0#)
• Four internal banks for concurrent operation
• Programmable burst lengths: 2, 4 or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs maximum average periodic refresh interval
MT9VDDT872A, MT18VDDT1672A
For the latest data sheet, please refer to the Micron Web
site:
www.micron.com/mti/msp/html/datasheet.html
PIN ASSIGNMENT
PIN SYMBOL PIN SYMBOL
1
V
REF
47
DQS8
2
DQ0
48
A0
3
V
SS
49
CB2
4
DQ1
50
V
SS
5
DQS0
51
CB3
6
DQ2
52
BA1
7
V
DD
53
DQ32
8
DQ3
54
V
DD
Q
9
NC
55
DQ33
10
NC
56
DQS4
11
V
SS
57
DQ34
12
DQ8
58
V
SS
13
DQ9
59
BA0
14
DQS1
60
DQ35
15
V
DD
Q
61
DQ40
16
CK1
62
V
DD
Q
17
CK1#
63
WE#
18
V
SS
64
DQ41
19
DQ10
65
CAS#
20
DQ11
66
V
SS
21
CKE0
67
DQS5
22
V
DD
Q
68
DQ42
23
DQ16
69
DQ43
24
DQ17
70
V
DD
25
DQS2
71
NC (S2#)
26
V
SS
72
DQ48
27
A9
73
DQ49
28
DQ18
74
V
SS
29
A7
75
CK2#
30
V
DD
Q
76
CK2
31
DQ19
77
V
DD
Q
32
A5
78
DQS6
33
DQ24
79
DQ50
34
V
SS
80
DQ51
35
DQ25
81
V
SS
36
DQS3
82
V
DDID
37
A4
83
DQ56
38
V
DD
84
DQ57
39
DQ26
85
V
DD
40
DQ27
86
DQS7
41
A2
87
DQ58
42
V
SS
88
DQ59
43
A1
89
V
SS
44
CB0
90
WP
45
CB1
91
SDA
46
V
DD
92
SCL
PIN SYMBOL PIN SYMBOL
93
V
SS
139
V
SS
94
DQ4
140
DQS17
95
DQ5
141
A10
96
V
DD
Q
142
CB6
97
DQS9
143
V
DD
Q
98
DQ6
144
CB7
99
DQ7
145
V
SS
100
V
SS
146
DQ36
101
NC
147
DQ37
102
NC
148
V
DD
103 NC (A13) 149
DQS13
104
V
DD
Q
150
DQ38
105
DQ12
151
DQ39
106
DQ13
152
V
SS
107
DQS10
153
DQ44
108
V
DD
154
RAS#
109
DQ14
155
DQ45
110
DQ15
156
V
DD
Q
111
CKE1
157
S0#
112
V
DD
Q
158
S1#
113 NC (BA2) 159
DQS14
114
DQ20
160
V
SS
115 NC (A12) 161
DQ46
116
V
SS
162
DQ47
117
DQ21
163
NC (S3#)
118
A11
164
V
DD
Q
119
DQS11
165
DQ52
120
V
DD
166
DQ53
121
DQ22
167 NC (FETEN)
122
A8
168
V
DD
123
DQ23
169
DQS15
124
Vss
170
DQ54
125
A6
171
DQ55
126
DQ28
172
V
DD
Q
127
DQ29
173
NC
128
V
DD
Q
174
DQ60
129
DQS12
175
DQ61
130
A3
176
V
SS
131
DQ30
177
DQS16
132
V
SS
178
DQ62
133
DQ31
179
DQ63
134
CB4
180
V
DD
Q
135
CB5
181
SA0
136
V
DD
Q
182
SA1
137
CK0
183
SA2
138
CK0#
184
V
DDSPD
OPTIONS
• Package
184-pin DIMM (gold)
MARKING
G
• Frequency/CAS Latency
266 MHz/CL = 2 (133 MHz DDR SDRAMs)
266 MHz/CL = 2.5 (133 MHz DDR SDRAMs)
200 MHz/CL = 2 (100 MHz DDR SDRAMs)
-262
-265
-202
184-Pin DIMM
NOTE:
Symbols in parentheses are not used on this module but may be
used for other modules in this product family. They are for reference
only.
8, 16 Meg x 72 DDR SDRAM DIMMs
ZM38.p65 – Rev. 3/00
1
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
DDR SDRAM DIMMs
KEY DDR SDRAM COMPONENT
TIMING PARAMETERS
MODULE
MARKING
-262/-265
-202
SPEED
GRADE
-7
-75
CLOCK FREQUENCY (1/
t
CK)
CL = 2*
CL = 2.5*
133 MHz
143 MHz
100 MHz
133 MHz
*CL = CAS (READ) latency
PART NUMBERS
PART NUMBER
CONFIGURATION SYSTEM BUS SPEED
MT9VDDT872AG-262__
8 Meg x 72
CL = 2, 266 MHz
MT9VDDT872AG-265__
8 Meg x 72
CL = 2.5, 266 MHz
MT9VDDT872AG-202__
8 Meg x 72
CL = 2, 200 MHz
MT18VDDT1672AG-262__
16 Meg x 72
CL = 2, 266 MHz
MT18VDDT1672AG-265__
16 Meg x 72
CL = 2.5, 266 MHz
MT18VDDT1672AG-202__
16 Meg x 72
CL = 2, 200 MHz
NOTE:
All part numbers end with a two-place code (not
shown), designating component and PCB revisions.
Consult factory for current revision codes. Example:
MT18VDDT1672AG-262A1
GENERAL DESCRIPTION
The MT9VDDT872A and MT18VDDT1672A are high-
speed CMOS, dynamic random-access, 64MB and 128MB
memories organized in a x72 configuration. These
modules use internally configured quad-bank DDR
SDRAMs.
These DDR SDRAM modules use a double data rate
architecture to achieve high-speed operation. The
double data rate architecture is essentially a 2n-prefetch
architecture with an interface designed to transfer two
data words per clock cycle at the I/O pins. A single read
or write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two correspond-
ing
n-bit
wide, one-half-clock-cycle data transfers at the
I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for WRITEs.
These DDR SDRAM modules operate from a differ-
ential clock (CK0 and CK0#); the crossing of CK0 going
HIGH and CK0# going LOW will be referred to as the
positive edge of CK0. Commands (address and control
signals) are registered at every positive edge of CK0.
Input data is registered on both edges of DQS, and
output data is referenced to both edges of DQS, as well
as to both edges of CK0.
Read and write accesses to the DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Accesses begin with the regis-
tration of an ACTIVE command, which is then fol-
lowed by a READ or WRITE command. The address bits
registered coincident with the ACTIVE command are
used to select the bank and row to be accessed. The
address bits registered coincident with the READ or
WRITE command are used to select the bank and the
starting column location for the burst access.
These DDR SDRAM modules provide for program-
mable READ or WRITE burst lengths of 2, 4 or 8
locations. An auto precharge function may be enabled
to provide a self-timed row precharge that is initiated at
the end of the burst access.
As with standard SDR SDRAM modules, the pipelined,
multibank architecture of DDR SDRAM modules allows
for concurrent operation, thereby providing high effec-
tive bandwidth by hiding row precharge and activation
time.
An auto refresh mode is provided, along with a
power-saving power-down mode. All inputs are com-
patible with the JEDEC Standard for SSTL_2. All outputs
are SSTL_2, Class II compatible. For more information
regarding DDR SDRAM operation, refer to the 64Mb x4,
x8 DDR SDRAM data sheet.
SERIAL PRESENCE-DETECT OPERATION
These DDR SDRAM modules incorporate serial pres-
ence-detect (SPD). The SPD function is implemented
using a 2,048-bit EEPROM. This nonvolatile storage
device contains 256 bytes. The first 128 bytes can be
programmed by Micron to identify the module type
and various SDRAM organizations and timing param-
eters. The remaining 128 bytes of storage are available
for use by the customer. System READ/WRITE opera-
tions between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard IIC bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA(2:0), which provide eight unique
DIMM/EEPROM addresses.
8, 16 Meg x 72 DDR SDRAM DIMMs
ZM38.p65 – Rev. 3/00
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT9VDDT872A (64MB)
RS0#
DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ0
DQ1 U9
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U13
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS7
DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ0
DQ1 U8
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U11
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS6
DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ0
DQ1 U16
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS5
DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ0
DQ1 U6
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ0
DQ1 U14
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
120
CK0
CK0#
SDRAM X 3
120
CK1
CK1#
SDRAM X 3
BA0, BA1
A0-A11
RAS#
CAS#
CKE0
WE#
BA0, BA1: SDRAMS U1,3,6,8,9,11,13,14,16
A0-A11: SDRAMS U1,3,6,8,9,11,13,14,16
RAS#: SDRAMS U1,3,6,8,9,11,13,14,16
CAS#: SDRAMS U1,3,6,8,9,11,13,14,16
CKE0: SDRAMS U1,3,6,8,9,11,13,14,16
WE#: SDRAMS U1,3,6,8,9,11,13,14,16
CK2
CK2#
120
SDRAM X 3
V
DDQ
SERIAL PD
SCL
WP
47K
A0
U20
A1 A2
SDA
V
DD
V
REF
V
SS
SDRAMS U1,3,6,8,9,11,13,14,16
SDRAMS U1,3,6,8,9,11,13,14,16
SDRAMS U1,3,6,8,9,11,13,14,16
SDRAMS U1,3,6,8,9,11,13,14,16
SA0 SA1 SA2
NOTE:
All resistor values are 22 ohms unless otherwise specified.
U1,3,6,8,9,11,13,14,16 = MT46V8M8TG DDR SDRAMs
8, 16 Meg x 72 DDR SDRAM DIMMs
ZM38.p65 – Rev. 3/00
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
DDR SDRAM DIMMs
FUNCTIONAL BLOCK DIAGRAM
MT18VDDT1672A (128MB)
RS1#
RS0#
DQS0
DQS9
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS1
DQS10
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQS2
DQS11
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQS3
DQS12
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS8
DQS17
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ0
DQ1 U9
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U18
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U4
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U13
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U3
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U12
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS7
DQS16
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM CS# DQS
DQ0
DQ1 U8
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U17
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U2
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U11
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS6
DQS15
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM CS# DQS
DQ0
DQ1 U7
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U16
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U10
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS5
DQS14
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM CS# DQS
DQ0
DQ1 U6
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U15
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQS4
DQS13
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DM CS# DQS
DQ0
DQ1 U5
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ0
DQ1 U14
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
120
CK0
CK0#
SDRAM X 6
120
CK1
CK1#
SDRAM X 6
BA0, BA1
A0-A11
RAS#
CAS#
CKE0
CKE1
WE#
BA0, BA1: SDRAMS U1-U18
A0-A11: SDRAMS U1-U18
RAS#: SDRAMS U1-U18
CAS#: SDRAMS U1-U18
CKE0: SDRAMS U1-U9
CKE1: SDRAMS U10-U18
WE#: SDRAMS U1-U18
V
DDQ
SERIAL PD
SDRAMS U1-U18
SDRAMS U1-U18
SDRAMS U1-U18
SDRAMS U1-U18
CK2
CK2#
120
SDRAM X 6
SCL
WP
47K
A0
U20
A1 A2
SDA
V
DD
V
REF
V
SS
SA0 SA1 SA2
NOTE:
All resistor values are 22 ohms unless otherwise specified.
U1-U18 = MT46V8M8TG DDR SDRAMs
8, 16 Meg x 72 DDR SDRAM DIMMs
ZM38.p65 – Rev. 3/00
4
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
ADVANCE
8, 16 MEG x 72
DDR SDRAM DIMMs
PIN DESCRIPTIONS
PIN NUMBERS
63, 65, 154
137, 138, 16, 17, 75, 76
SYMBOL
WE#, CAS#,
RAS#
CK0, CK0#, CK1,
CK1#, CK2#, CK2
TYPE
Input
Input
DESCRIPTION
Command Inputs: WE#, RAS#, and CAS# (along with
S0#, S1#) define the command being entered.
Clocks: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge
of CK#. Output data (DQs and DQS) is referenced to
the crossings of CK and CK#.
Clock Enables: CKE0 and CKE1 activate (HIGH) and
deactivate (LOW) internal clock signals, and device input
buffers and output drivers. Deactivating the clock
provides PRECHARGE POWER-DOWN and SELF REFRESH
operation (all banks idle), or ACTIVE POWER-DOWN
(row ACTIVE in any bank). CKE0 and CKE1 are synchro-
nous for all functions except for disabling outputs,
which is achieved asynchronously. CKE0 and CKE1 must
be maintained HIGH throughout read and write
accesses. Input buffers (excluding CK0, CK0# and CKE)
are disabled during POWER-DOWN. Input buffers
(excluding CKE0 and CKE1) are disabled during SELF
REFRESH. CKE0 and CKE1 are SSTL_2 inputs but will
detect an LVCMOS LOW level after V
DD
is applied.
Chip Selects: S0# and S1# enable (registered LOW) and
disable (registered HIGH) the command decoder. All
commands are masked when S0# and S1# are registered
HIGH. S0# and S1# provide for external bank selection
on systems with multiple banks. S0# and S1# are
considered part of the command code.
Bank Addresses: BA0 and BA1 define to which bank an
ACTIVE, READ, WRITE or PRECHARGE command is being
applied.
Address Inputs: A0-A11 are sampled during the ACTIVE
command (row-address A0-A11) and READ/WRITE
command (column-address A0-A8, with A10 defining
auto precharge) to select one location out of the
memory array in the respective bank. A10 is sampled
during a PRECHARGE command to determine whether
the PRECHARGE applies to one bank (A10 LOW) or all
banks (A10 HIGH). The address inputs also provide the
op-code during a MODE REGISTER SET command.
SSTL_2 reference voltage.
V
DD
identification flag.
Write Protect: Serial presence-detect hardware write
protect.
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
21, 111
CKE0, CKE1
Input
157, 158
S0#, S1#
Input
59, 52
BA0, BA1
Input
48, 43, 41, 130, 37, 32,
125, 29, 122, 27, 141,
118
A0-A11
Input
1
82
90
92
V
REF
V
DDID
WP
SCL
Input
Input
Input
Input
8, 16 Meg x 72 DDR SDRAM DIMMs
ZM38.p65 – Rev. 3/00
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2000, Micron Technology, Inc.
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