HIGH-SPEED 32K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
Features
x
x
PRELIMINARY
IDT70927S/L
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
High-speed clock to data access
Commercial: 20/25/30ns
Low-power operation
IDT70927S
Active: 950mW (typ.)
Standby: 5mW (typ.)
IDT70927L
Active: 950mW (typ.)
Standby: 1mW (typ.)
Flow-Through output mode
Counter enable and reset features
Dual chip enables allow for depth expansion without
additional logic
x
x
x
x
x
Full synchronous operation on both ports
4ns setup to clock and 1ns hold on all control, data,
and address inputs
Data input, address, and control registers
Fast 20ns clock to data out
Self-timed write allows fast cycle time
25ns cycle time, 40MHz operation
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
TTL- compatible, single 5V (±10%) power supply
Industrial temperature range (40°C to +85°C) is available
for selected speeds
Available in 108-pin Pin Grid Array (PGA) and 100 pin Thin
Quad Flatpack (TQFP) packages
Functional Block Diagram
R/W
L
UB
L
CE
0L
CE
1L
LB
L
OE
L
R/W
R
UB
R
CE
0R
CE
1R
LB
R
OE
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
I/O
Control
I/O
Control
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
A
14L
A
0L
CLK
L
ADS
L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
MEMORY
ARRAY
Counter/
Address
Reg.
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
3201 drw 01
JUNE 1999
1
©1999 Integrated Device Technology, Inc.
DSC-3201/7
IDT70927S/L
High-Speed 32K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
The IDT70927 is a high-speed 32K x 16 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.
Description
With an input data register, the IDT70927 has been optimized for
applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by
CE
0
and CE
1,
permits
the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDTs CMOS high-performance technology,
these devices typically operate on only 950mW of power.
Pin Configurations
(1,2,3)
Index
A
9L
A
10L
A
11L
A
12L
A
13L
A
14L
NC
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
Vcc
R/W
L
OE
L
GND
GND
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
1
75
2
74
3
73
72
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
A
8L
A
7L
A
6L
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
CNTEN
L
CLK
L
ADS
L
GND
ADS
R
CLK
R
CNTEN
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
IDT70927PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
51
25
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
9R
A
10R
A
11R
A
12R
A
13R
A
14R
NC
NC
NC
LB
R
UB
R
CE
0R
CE
1R
CNTRST
R
GND
R/W
R
OE
R
GND
GND
I/O
15R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
I/O
10R
,
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
I/O
9L
I/O
8L
Vcc
I/O
7
L
I/O
6L
I/O
5L
I/O
4L
I/O
3L
I/O
2L
GND
I/O
IL
I/O
0L
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
I/O
4R
I/O
5R
I/O
6R
Vcc
I/O
7R
I/O
8R
I/O
9R
NC
3201drw 02
2
6.42
IDT70927S/L
High-Speed 32K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Pin Configurations (con't.)
(1,2)
81
80
77
74
72
69
12
11
A
10R
84
A
11R
83
A
14R
78
NC
76
UB
R
73
CNT
RST
R
68
65
63
60
57
54
GND
67
GND
64
NC
61
I/O
13R
I/O
10R
59
56
NC
53
70
A
7R
87
A
8R
86
A
13R
82
NC
79
LB
R
75
CE
1R
R/W
R
71
66
GND I/O
14R
I/O
12R
I/O
9R
62
58
55
51
NC
50
10
A
4R
90
A
5R
88
A
9R
85
A
12R
NC
CE
0R
OE
R
I/O
15R
I/O
11R
NC
52
I/O
8R
49
I/O
7R
47
09
08
A
1R
92
A
3R
91
A
6R
89
NC
48
Vcc
46
I/O
5R
45
CNT
EN
R
95
A
0R
94
A
2R
93
I/O
6R
44
I/O
4R
43
I/O
3R
42
07
06
GND
96
ADS
R
CLK
R
97
98
IDT70927PF
G108-1
(4)
108-Pin PGA
Top View
(5)
I/O
2R
39
I/O
1R
40
I/O
0R
41
ADS
L
99
CLK
L
100
CNT
EN
L
102
I/0
1L
35
I/O
0L
37
GND
38
05
04
03
A
0L
101
A
1L
103
A
3L
106
I/O
4L
31
I/O
2L
34
GND
36
A
2L
104
A
4L
105
1
A
7L
4
8
12
17
21
25
Vcc
28
I/O
5L
32
I/O
3L
33
A
5L
107
2
A
6L
5
A
10L
7
A
13L
NC
10
CE
1L
13
GND
16
I/O
14L
I/O
10L
19
22
NC
24
I/O
7L
29
I/O
6L
30
02
A
8L
108
3
A
11L
A
12L
B
A
14L
6
9
NC
LB
L
D
UB
L
11
CNT
RST
L
14
OE
L
15
GND I/O
13L
18
20
I/O
11L
23
NC
26
I/O
8L
27
01
A
9L
A
NC
C
CE
0L
E
Vcc
F
R/W
L
G
NC
H
I/O
15L
J
I/O
12L
K
I/O
9L
L
NC
M
3201 drw 03
,
Index
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21in x 1.21in x 0.16in
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port
CE
0L
, CE
1L
R/W
L
OE
L
A
0L
- A
14L
I/O
0L
- I/O
15L
CLK
L
UB
L
LB
L
ADS
L
CNTEN
L
CNTRST
L
Right Port
CE
0R
, CE
1R
R/W
R
OE
R
A
0R
- A
14R
I/O
0R
- I/O
15R
CLK
R
UB
R
LB
R
ADS
R
CNTEN
R
CNTRST
R
V
CC
GND
Names
Chip Enables
Read/Write Enable
Output Enable
Address
Data Input/Output
Clock
Upper Byte Select
Lower Byte Select
Address Strobe
Counter Enable
Counter Reset
Power
Ground
3201 tbl 01
6.42
3
IDT70927S/L
High-Speed 32K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Truth Table IRead/Write and Enable Control
(1,2,3)
OE
X
X
X
X
X
X
L
L
L
H
CLK
↑
↑
↑
↑
↑
↑
↑
↑
↑
X
CE
0
H
X
L
L
L
L
L
L
L
L
CE
1
X
L
H
H
H
H
H
H
H
H
UB
X
X
H
L
H
L
L
H
L
L
LB
X
X
H
H
L
L
H
L
L
L
R/
W
X
X
X
L
L
L
H
H
H
X
Upper
Byte
I/O
8-15
High-Z
High-Z
High-Z
D
IN
High-Z
D
IN
D
OUT
High-Z
D
OUT
High-Z
Lower B
yte
I/O
0-7
High-Z
High-Z
High-Z
High-Z
D
IN
D
IN
High-Z
D
OUT
D
OUT
High-Z
Mode
DeselectedPower Down
DeselectedPower Down
Both Bytes Deselected
Write to Upper Byte Only
Write to Lower Byte Only
Write to Both Bytes
Read Upper Byte Only
Read Lower Byte Only
Read Both Bytes
Outputs Disabled
3201 tbl 02
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST
= X.
3.
OE
is an asynchronous input signal.
TRUTH TABLE IIADDRESS COUNTER CONTROL
(1,2)
Address
X
An
X
X
Previous
Address
X
X
An
An
CLK
↑
↑
↑
↑
ADS
H
L
(3)
H
H
CNTEN
H
H
H
L
(4)
CNTRST
L
H
H
H
I/O
D
I/O
(0)
D
I/O
(n)
D
I/O
(n)
D
I/O
(n+1)
Mode
Counter Reset to Address 0
External Address Utilized
External Address BlockedCounter Disabled
Counter EnableInternal Address Generation
3201 tbl 03
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB,
and
OE
= V
IL
; CE
1
and R/W = V
IH
.
3.
ADS
is independent of all other signals including
CE
0
, CE
1
,
UB
and
LB.
4. The address counter advances if
CNTEN
= V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB
and
LB.
4
6.42
IDT70927S/L
High-Speed 32K x 16 Synchronous Dual-Port Static RAM
Preliminary
Industrial and Commercial Temperature Ranges
Recommended Operating
Recommended DC Operating
(1,2)
Temperature and Supply Voltage
Conditions
Grade
Commercial
Industrial
Ambient
Temperature
0 C to +70 C
O
O
GND
0V
0V
Vcc
5.0V
+
10%
5.0V
+
10%
3201 tbl 04
Symbol
V
CC
GND
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min.
4.5
0
2.2
-0.5
(2)
Typ.
5.0
0
____
____
Max.
5.5
0
6.0
(1)
0.8
Unit
V
V
V
V
3201 tbl 05
-40 C to +85 C
O
O
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1. V
TERM
must not exceed V
cc
+ 10%.
2. V
IL
> -1.5V for pulse width less than 10ns.
Absolute Maximum Ratings
(1)
Symbol
V
TERM
(2)
Rating
Terminal Voltage
with Respect
to GND
Temperature
Under Bias
Storage
Temperature
DC Output
Current
Commercial
& Industrial
-0.5 to +7.0
Unit
V
CAPACITANCE
(1)
Symbol
C
IN
C
OUT
(3)
Parameter
Input Capacitance
Output Capacitance
(T
A
= +25°C, f = 1.0MH
z
) TQFP Only
Conditions
(2)
V
IN
= 3dV
V
OUT
= 3dV
Max.
9
10
Unit
pF
pF
3201 tbl 07
T
BIAS
T
STG
I
OUT
-55 to +125
-55 to +125
50
o
C
C
o
mA
3201 tbl 06
NOTES:
1. These parameters are determined by device characterization, but are not produc-
tion tested.
2. 3dV references the interpolated capacitance when the input and output switch from
0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
cc
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 10%.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(V
CC
= 5.0V ± 10%)
70927S/L
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
(1)
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Conditions
V
CC
= 5.5V, V
IN
= 0V to V
CC
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
I
OL
= +4mA
I
OH
= -4mA
Min.
___
___
___
Max.
10
10
0.4
___
Unit
µA
µA
V
V
3201 tbl 08
2.4
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
6.42
5
分立器件
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
