TRAILING EDGE PRODUCT - MINIMUM ORDER APPLIES
PRODUCT MAY BE MADE OBSOLETE WITHOUT NOTICE
128K x 8 SRAM
MSM8128A - 85/10/12
Elm Road, West Chirton, NORTH SHIELDS, Tyne & Wear
NE29 8SE, England Tel. +44 (0191) 2930500 Fax. +44 (0191) 2590997
Issue 1.0 April 2001
Description
The MSM8128 is a 1Mbit monolithic SRAM
organised as 128K x 8. It is available in with
access times of 85, 100 & 120ns. It has a low
power standby version and has 3.0V battery
backup capability. It is directly TTL compatible
and has common data inputs and outputs.
Two pinout variants (single and dual CS) are
available.
All versions may be screened in accordance with
MIL-STD-883.
131,072 x 8 CMOS Static RAM
Features
Access Times of 85/100/120 ns
JEDEC standard Dual CS footprints.
Operating Power
605 mW (max)
Low Power Standby (-L) 2.53 mW (max)
Low Voltage Data Retention.
Completely Static Operation
Directly TTL compatible.
May be processed in accordance with MIL-STD-883
Block Diagram
Pin Definition
MEMORY ARRAY
A0
A1
A2
D0
A3
A4
A5
A6
7
6
512 X 2048
13
12
11
10
9
8
5
D1
D2
GND
D3
D4
D5
D6
14
15
16
17
18
19
20
4
3
2
1
32
31
30
A12
A14
A16
NC
VCC
A15
CS2
TOP VIEW
J
21
22
23
24
25
26
27
28
A8
A13
29
WE
CS1
A10
OE
Package Details
Pin Count
Description
Package Type
32
LCC (0.45 x 0.55" nom)
W
Package details on pages 8 & 9.
See Page 9 for X pinout
Pin Functions
A0-A16
Address Inputs
D0-7
Data Input/Output
CS1
Chip Select 1
CS2
Chip Select 2
OE
Output Enable
WE
Write Enable
NC
No Connect
V
CC
Power (+5V)
GND
Ground
A11
A9
D7
A7
MSM8128 - 70/85/10/12
Issue 1.0 April 2001
DC OPERATING CONDITIONS
Absolute Maximum Ratings
Voltage on any pin relative to V
SS
Power Dissipation
Storage Temperature
Notes :
V
T
P
T
T
STG
-0.5V
-55
to
1
to
+7.0
+150
V
W
o
C
(1) Stresses above those listed may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operating Conditions
min
Supply Voltage
Input High Voltage
Input Low Voltage
Operating Temperature
V
CC
V
IH
V
IL
T
A
T
AI
T
AM
4.5
2.2
-0.3
0
-40
-55
typ
5.0
-
-
-
-
-
max
5.5
5.8
0.8
70
85
125
V
V
V
o
C
o
C (I suffix)
o
C (M,
MB
suffix)
DC Electrical Characteristics
(V
CC
= 5.0V±10%, T
A
=-55°C to +125°C)
Parameter
Input Leakage Current
Output Leakage Current
Average Supply Current
Standby Supply Current
-L Part
Output Voltage
Symbol
I
LI
I
l/O
I
CC1
I
SB1
I
SB2
V
OL
V
OH
Test Condition
V
IH
=0V to V
cc
CS1=V
IH
, CS2 =V
IL
, V
I/O
=0V to V
cc
,OE=V
IH
Min. Cycle, V
IN
=V
IL
or V
IH
CS1=V
IH
,CS2 = V
IL
, I/P's static
CS1
≥
V
CC
-0.2V, 0.2V
≥
CS2
≥
V
CC
-0.2V , V
IN
≥
0.2V
I
OL
= 2.1 mA
I
OH
= -1.0 mA
min
-1
-1
-
-
-
-
2.4
typ
-
-
-
-
-
-
-
max Unit
1
1
110
3.5
460
0.4
-
µA
µA
mA
mA
uA
V
V
Capacitance
(V
CC
=5V±10%,T
A
=25
o
C)
Parameter
I/P Capacitance
I/O Capacitance
Symbol
C
IN
C
I/O
Test Condition
V
IN
=0V
V
I/O
=0V
typ
-
-
max
8
10
Unit
pF
pF
Note: This parameter is sampled and not 100% tested.
2
MSM8128 - 70/85/10/12
Issue 1.0 April 2001
Operating Modes
The table below shows the logic inputs required to control the MSM8128 SRAM.
Mode
Not Selected
Not Selected
Output Disable
Read
Write
CS1
1
X
0
0
0
CS2
X
0
1
1
1
OE
X
X
1
0
X
WE
X
X
1
1
0
V
CC
Current
I
SB1
,I
SB2
I
SB
,I
SB1
I
CC
I
CC
I
CC
X = Don't Care
I/O Pin
High Z
High Z
High Z
D
OUT
D
IN
Reference Cycle
Power Down
Power Down
Read Cycle
Write Cycle
1 = V
IH
,
0 = V
IL
,
Low V
cc
Data Retention Characteristics - L Version Only
(T
A
=-55°C to +125
o
C)
Parameter
V
CC
for Data Retention
Data Retention Current
Symbol Test Condition
V
DR
I
CCDR
CS1
≥
V
CC
-0.2V, CS2
≥
V
CC
-0.2V or
0V
≤
CS2
≤
0.2V. V
IN
≥
0V
V
CC
=3.0V,V
IN
≥
0V, CS1
≥
V
CC
-0.2V,
CS2
≥
V
CC
-0.2V or 0V
≤
CS2
≤
0.2V.
See Retention Waveform
See Retention Waveform
min
2.0
-
0
5
typ
-
-
-
-
max
-
700
-
-
Unit
V
µA
ns
ms
Chip Deselect to Data Retention t
CDR
Operation Recovery Time
t
R
Notes (1) CS2 controls address buffer, WE buffer, CS1 buffer and OE buffer. If CS2 controls data retention mode,
Vin levels (WE,OE,CS1,I/O) can be in the high impedance state. If CS1 controls Data Retention mode,
CS2 must be
≥
V
CC
- 0.2V or 0V
≤
CS2
≤
0.2V. The other input levels (address, WE,OE,I/O) can be in the
high impedance state.
AC Test Conditions
* Input pulse levels: 0V to 3.0V
* Input rise and fall times: 5ns
* Input and Output timing reference levels: 1.5V
* Output load: See Load Diagram
* V
cc
=5V±10%
Output Load
I/O Pin
166
Ω
1.76V
30pF
3
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
9876543210987654321
MSM8128 - 70/85/10/12
Write to Output in High Z
Data to Write Time Overlap
Data Hold from Write Time
Output Active from End of Write
Write Cycle Time
Chip Selection to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time (WE, CS1)
Read Cycle Time
Address Access Time
Chip Select (CS1) Access Time
(2)
Chip Select (CS2) Access Time
(2)
Output Enable to Output Valid
Output Hold from Address Change
Chip Selection (CS1) to Output in Low Z
Chip Selection (CS2) to Output in Low Z
Output Enable to Output in Low Z
Chip Disable (CS1) to Output in High Z
(3)
Chip Disable (CS2) to Output in High Z
(3)
Output Disable to Output in High Z
(3)
Parameter
Parameter
AC OPERATING CONDITIONS
Write Cycle
Read Cycle
(CS2)
Consult Factory
Symbol
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
WR1
t
WR2
t
WHZ
t
DW
t
DH
t
OW
t
RC
t
AA
t
ACS1
t
ACS2
t
OE
t
OH
t
CLZ1
t
CLZ2
t
OLZ
t
CHZ1
t
CHZ2
t
OHZ
70
min max
70
min max
70
60
60
0
50
5
5
0
30
0
5
70
-
-
-
-
5
10
10
5
0
0
0
4
543210987654321
543210987654321
543210987654321
543210987654321
543210987654321
543210987654321
-
70
70
70
35
-
-
-
-
35
35
30
-
-
-
-
-
-
-
30
-
-
-
85
min max
85
min max
85
-
-
-
-
5
10
10
5
0
0
0
-
85
85
85
45
-
-
-
-
35
35
30
85
75
75
0
60
5
5
0
35
0
5
-
-
-
-
-
-
-
30
-
-
-
100
85
85
0
70
5
5
0
40
0
5
100
-
-
-
-
10
10
10
5
0
0
0
10
min max
10
min max
-
100
100
100
50
-
-
-
-
35
35
35
-
-
-
-
-
-
-
35
-
-
-
120
100
100
0
70
5
5
0
45
0
5
120
-
-
-
-
10
10
10
5
0
0
0
12
min max Unit
12
min max Unit
Issue 1.0 April 2001
-
120
120
120
60
-
-
-
-
45
45
45
-
-
-
-
-
-
-
40
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MSM8128 - 70/85/10/12
Issue 1.0 April 2001
Read Cycle Timing Waveform
(1,2 )
t
RC
Address
t
AA
OE
t
OE
t
OLZ
t
CLZ1
t
ACS1 (2)
t
CHZ1 (3)
t
OH
CS1
CS2
t
ACS2 (2)
t
CLZ2
t
OHZ (3)
Dout
Data Valid
t
CHZ2 (3)
Notes:
(1) WE is High for Read Cycle.
(2) Address valid prior to or coincident with CS1 transition low or CS2 high.
(3) t
CHZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not
referenced to output voltage levels. At any given temperature and voltage condition, t
CHZ
max is less than
t
CLZ
min both for a given device and from device to device. This parameter is sampled and not 100% tested.
5
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
