DATASHEET
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
Description
The MK2059-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock generator that produces common
telecommunications reference frequencies. The output
clock is phase locked to an 8kHz (frame rate) input
reference clock. The MK2059-01 also provides jitter
attenuation. Included in the selection of output frequencies
are these common system clocks:
1.544 MHz (T1)
19.44 MHz (OC-3)
2.048 (E1)
16.384 MHz (8x E1)
MK2059-01
Features
•
Generates T1, E1, OC-3 and other common telecom
•
•
•
•
•
•
•
•
•
•
•
clock frequencies from an 8kHz frame clock
Configurable jitter attenuation characteristics, excellent
for use as a Stratum source de-jitter circuit
2:1 Input MUX for input reference clocks
VCXO-based clock generation offers very low jitter and
phase noise generation
Output clock is phase and frequency locked to the
selected input reference clock
Fixed input to output phase relationship (except for 1.544
MHz and 2.048 MHz output selections)
+115ppm minimum crystal frequency pullability range,
using recommended crystal
Industrial temperature range
Low power CMOS technology
20 pin SOIC package
Single 3.3V power supply
Available in Pb (lead) free package
This monolithic IC, combined with an external inexpensive
quartz crystal, can be used to replace a more costly hybrid
VCXO retiming module. Through selection of external loop
filter components, the PLL loop bandwidth and damping
factor can be tailored to meet input clock jitter attenuation
requirements. A loop bandwidth down to the Hz range is
possible
NOTE: EOL for non-green parts to occur on 5/13/10
per PDN U-09-01
Block Diagram
Pullable Crystal
ISET
X1
X2
VDD
VDD
3
8kHz Ref Input ICLK2
8kHz Ref Input ICLK1
ISEL
1
0
Phase
Detector
Charge
Pump
VCXO
Output
Divider
CLK
Feedback
Divider
SEL2:0
3
CHGP
VIN
GND
4
IDT™
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
1
MK2059-01
REV G 122109
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
VCXO AND SYNTHESIZER
Pin Assignment
X1
VD D
VD D
VD D
V IN
GND
GND
GND
CHG P
IS E T
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
GND
IS E L
IC L K 1
IC L K 2
SEL0
CLK
NC
SEL1
SEL2
Output Clock Selection Table
Input
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
8 kHz
SEL2
0
0
0
0
M
M
M
M
1
1
1
1
SEL1
0
0
1
1
0
0
1
1
0
0
1
1
SEL0
0
1
0
1
0
1
0
1
0
1
0
1
Output
Clock
(MHz)
1.544
2.048
16.384
17.664
18.528
20.00
25.00
25.92
19.44
20.48
24.704
24.576
Crystal
Used (MHz)
24.704
24.576
16.384
17.664
18.528
20.00
25.00
25.92
19.44
20.48
24.704
24.576
20 pin 300 mil SOIC
Note: For SEL input pin programming:
0 = GND, 1 = VDD, M = Floating
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
X1
VDD
VDD
VDD
VIN
GND
GND
GND
CHGP
ISET
SEL2
SEL1
NC
CLK
SEL0
ICLK2
ICLK1
ISEL
GND
X2
Pin
Type
-
Power
Power
Power
Input
Power
Power
Power
Output
-
Input
Input
Input
Output
Input
Input
Input
Input
Power
-
Pin Description
Crystal Input. Connect this pin to the specified crystal.
Power Supply. Connect to +3.3V.
Power Supply. Connect to +3.3V.
Power Supply. Connect to +3.3V.
VCXO Control Voltage Input. Connect this pin to CHGP pin and the external
loop filter as shown in this data sheet.
Connect to ground
Connect to ground
Connect to ground
Charge Pump Output. Connect this pin to the external loop filter and to pin
VIN.
Charge pump current setting node, connection for setting resistor.
Output Frequency Selection Pin 2. Determines output frequency as per table
above. Internally biased to VDD/2.
Output Frequency Selection Pin 1. Determines output frequency as per table
above. Internal pull-up.
No Internal Connection.
Clock Output
Output Frequency Selection Pin 0. Determines output frequency as per table
above. Internal pull-up.
Input Clock Connection 2. Connect an input reference clock to this pin. If
unused, connect to ground.
Input Clock Connection 1. Connect an input reference clock to this pin. If
unused, connect to ground.
Input Selection. Used to select which reference input clock is active. Low input
level selects ICLK1, high input level selects ICLK2. Internal pull-up.
Connect to ground.
Crystal Output. Connect this pin to the specified crystal.
IDT™
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
2
MK2059-01
REV G 122109
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
VCXO AND SYNTHESIZER
Functional Description
The MK2059-01 is a clock generator IC that generates an
output clock directly from an internal VCXO circuit which
works in conjunction with an external quartz crystal. The
VCXO is controlled by an internal PLL (Phase Locked Loop)
circuit, enabling the device to perform clock regeneration
from an input reference clock. The MK2059-01 is configured
to provide a MHz communications reference clock output
from an 8kHz input clock. There are 12 selectable output
frequencies. Please refer to the Output Clock Selection
Table on Page 2.
Most typical PLL clock devices use an internal VCO (Voltage
Controlled Oscillator) for output clock generation. By using
a VCXO with an external crystal, the MK2059-01 is able to
generate a low jitter, low phase-noise output clock within a
low bandwidth PLL. This serves to provide input clock jitter
attenuation and enables stable operation with a low
frequency reference clock.
The VCXO circuit requires an external pullable crystal for
operation. External loop filter components enable a PLL
configuration with low loop bandwidth.
Quartz Crystal
It is important that the correct type of quartz crystal is used
with the MK2059-01. Failure to do so may result in reduced
frequency pullability range, inability of the loop to lock, or
excessive output phase jitter.
The MK2059-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input. The
VCXO consists of the external crystal and the integrated
VCXO oscillator circuit. To achieve the best performance
and reliability, a crystal device with the recommended
parameters (shown below) must be used, and the layout
guidelines discussed in the PCB Layout Recommendations
section must be followed.
The frequency of oscillation of a quartz crystal is determined
by its cut and by the external load capacitance. The
MK2059-01 incorporates variable load capacitors on-chip
which “pull”, or change, the frequency of the crystal. The
crystals specified for use with the MK2059-01 are designed
to have zero frequency error when the total of on-chip +
stray capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2059-01 and the crystal.
A complete description of the recommended crystal
parameters is shown in application note MAN05.
Application Information
Output Frequency Configuration
The MK2059-01 is configured to generate a set of output
frequencies from an 8kHz input clock. Please refer to the
Output Clock Selection Table on Page 2. Input bits SEL2:0
are set according to this table, as is the external crystal
frequency. Please refer to the Quartz Crystal section on this
page regarding external crystal requirements.
A list of qualified crystal devices that meet these
requirements can be found on the IDT web site.
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish operating
stability. The MK2059-01 uses external loop filter
components for the following reasons:
1) Larger loop filter capacitor values can be used, allowing
a lower loop bandwidth. This enables the use of lower input
clock reference frequencies and also input clock jitter
attenuation capabilities. Larger loop filter capacitors also
allow higher loop damping factors when less passband
peaking is desired.
2) The loop filter values can be user selected to optimize
loop response characteristics for a given application.
Referencing the External Component Schematic on this
page, the external loop filter is made up of components R
S
,
C
S
and C
P
. R
SET
establishes PLL charge pump current and
therefore influences loop filter characteristics. Tools for
determining loop filter component values are on the IDT web
site.
Input Mux
The Input Mux serves to select between two alternate input
reference clocks. Upon reselection of the input clock, clock
glitches on the output clock will not be generated due to the
“fly-wheel” effect of the VCXO (the quartz crystal is a high-Q
tuned circuit). When the input clocks are not phase aligned,
the phase of the output clock will change to reflect the phase
of newly selected input at a controlled phase slope (rate of
phase change) as influenced by the PLL loop
characteristics.
IDT™
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
3
MK2059-01
REV G 122109
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
VCXO AND SYNTHESIZER
External Component Schematic
C
L
Don't Stuff
(Refer to
Optional Crystal
Tuning section)
X1
VDD
VDD
VDD
VIN
C
L
Crystal
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
GND
ISEL
ICLK1
ICLK2
SEL0
CLK
NC
SEL1
SEL2
C
P
R
S
C
S
GND
GND
GND
CHGP
ISET
R
SET
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Crystal
SEL2 SEL1 SEL0
Multiplier
(N)
0
0
0
3088
0
0
1
3072
0
1
0
2048
0
1
1
2208
M
0
0
2316
M
0
1
2500
M
1
0
3125
M
1
1
3240
1
0
0
2430
1
0
1
2560
1
1
0
3088
1
1
1
3072
R
SET
R
S
C
S
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
C
P
Loop
Bandwidth
(-3dB point)
Damping
Factor
1.4
1.4
1.7
1.7
1.6
1.6
1.4
1.4
1.6
1.6
1.4
1.4
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
120 kΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
1.0 MΩ
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
18 Hz
19 Hz
27 Hz
26 Hz
24 Hz
22 Hz
18 Hz
17 Hz
23 Hz
22 Hz
18 Hz
19 Hz
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
IDT™
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
4
MK2059-01
REV G 122109
MK2059-01
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
VCXO AND SYNTHESIZER
A “normalized” PLL loop bandwidth may be calculated as
follows:
R
S
×
I
CP
×
575
NBW
= -----------------------------------------
N
Special considerations must be made in choosing loop
components C
S
and C
P
. These recommendations can be
found on the IDT web site.
The “normalized” bandwidth equation above does not take
into account the effects of damping factor or the second
pole. However, it does provide a useful approximation of
filter performance.
The loop damping factor is calculated as follows:
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a commonly
used trace impedance), place a 33Ω resistor in series with
the clock line, as close to the clock output pin as possible.
The nominal impedance of the clock output is 20Ω (The
.
optional series termination resistor is not shown in the
External Component Schematic.)
Damping Factor = R
S
×
625
×
I
CP
×
C
S
------------------------------------------
-
N
Decoupling Capacitors
Where:
R
Z
= Value of resistor in loop filter (Ohms)
I
CP
= Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C
1
= Value of capacitor C
1
in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C
1
and C
2
in the loop
filter:
As with any high performance mixed-signal IC, the
MK2059-01 must be isolated from system power supply
noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To further
guard against interfering system supply noise, the
MK2059-01 should use one common connection to the PCB
power plane as shown in the diagram on the next page. The
ferrite bead and bulk capacitor help reduce lower frequency
noise in the supply that can lead to output clock phase
modulation.
C
P
=
-----
-
20
C
S
Recommended Power Supply Connection for
Optimal Device Performance
V D D P in
C onnection to 3.3V
P ow er P lane
Ferrite
Bead
V D D P in
Charge Pump Current Table
R
SET
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
Charge Pump Current
(I
CP
)
10
µA
20
µA
25
µA
100
µA
B ulk D ecoupling C apacitor
(such as 1 F Tantalum )
V D D P in
0.01
F D ecoupling C apacitors
IDT™
VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR
5
MK2059-01
REV G 122109
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