synthesizer designed to replace expensive discrete
VCXOs and oscillators. The on-chip Voltage
Controlled Crystal Oscillator (VCXO) accepts a
0 to 3.3 V input voltage to cause the output clocks
to vary by ±100 ppm. Using ICS’s patented
VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive 10 MHz
to 18 MHz pullable crystal input to produce one
or two output clocks. To achieve lowest phase
noise, the REFCLK can be turned off.
ICS manufactures the largest variety of clocks for
set-top boxes and Communications. Consult ICS
to eliminate VCXOs, crystals, oscillators and
buffers from your board.
Block Diagram
REFEN
2
S1, S0
PLL/Clock
Synthesis
Circuitry
Voltage
Controlled
Crystal
Oscillator
Output
Buffer
CLK
VIN
10-18 MHz
X1
pullable
crystal
X2
Output
Buffer
REFCLK
OE (both outputs)
1
Revision 082800
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 3732-15 A
PRELIMINARY INFORMATION
MK3732-15
Low Phase Noise VCXO+Multiplier
Clock Select Table
S2
0
0
0
0
0
0
1
1
1
1
1
1
S1
0
0
0
1
1
1
0
0
0
1
1
1
S0
0
M
1
0
M
1
0
M
1
0
M
1
CLK
REF/2
x0.666
x2.6666
x4
x1.5
x1.3333
Test
x4
x2
x3
x5
x6
Pin Assignment
MK3732-15
X1
VDD
VDD
VIN
GND
GND
S2
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
X2
S1
REFCLK
GND
CLK
VDD
REFEN
S0
For Analog Devices’
ADSL chipset, use a
17.664 MHz crystal,
and the 101 setting
for a 35.328 MHz
output clock. Pin 10
should be grounded
to get the 17.664 MHz
clock output on pin 14.
16 pin (173 mil) TSSOP
Pin Descriptions
Number
1
2, 3, 11
4
5, 6, 13
7
8
9
10
12
14
15
16
Name
X1
VDD
VIN
GND
S2
OE
S0
REFEN
CLK
REFCLK
S1
X2
Type
XI
P
VI
P
I
I
TI
I
O
O
I
XO
0 = connect directly to GND, M = leave unconnected
(floating), 1 = connect directly to VDD.
Description
Crystal connection. Connect to a pullable crystal of 10-18 MHz.
VDD. Connect to +3.3V.
Voltage Input to VCXO. Zero to 3.3 V signal which controls the frequency of the VCXO.
Connect to ground.
Select input #2. Selects CLK output per table above.
Output Enable. Tri-states outputs when low.
Select input #0. Selects CLK output per table above.
Reference Enable (active low). When pin is connected to ground, the REFCLK is running.
VCXO Clock Output per table above.
Buffered crystal VCXO clock
Select input #1. Selects CLK output per table above.
Crystal connection. Connect to a pullable crystal of 10-18 MHz.
Key: I = Input with internal pull-up resistor; TI = tri-level input; O = output; P = power supply connection;
VI = analog voltage input; XI, XO = crystal pins.
External Components
The MK3732-15 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD and GND on pins 3 and 5, and VDD and GND
on pins 11 and 13, as close to the MK3732-15 as possible. A series termination resistor of 33
Ω
may be used
for each clock output. The input crystal must be connected as close to the chip as possible. The input crystal
should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load capacitance is
recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT - consult the
application note MAN05 for layout guidelines.
2
Revision 082800
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 3732-15 A
PRELIMINARY INFORMATION
MK3732-15
Low Phase Noise VCXO+Multiplier
Minimum
Typical
Maximum
7
VDD+0.5
70
260
150
3.30
2.5
2.5
3.45
1.5
0.8
VDD-0.5
0.5
2.4
0.4
VDD-0.4
9
±50
5
0
10
0
3.3
18
1.5
1.5
60
±150
-115
±100
Units
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
V
V
mA
mA
pF
ppm
V
MHz
ns
ns
%
ps
dBc/Hz
ppm
Electrical Specifications
Parameter
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Core Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH, binary input
Input Low Voltage, VIL, binary input
Input High Voltage, VIH, trinary inputs
Input Low Voltage, VIL, trinary inputs
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
Input Crystal Frequency
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
Maximum Absolute Jitter, short term
Phase Noise, relative to carrier, note 3
Output pullability, note 2
Notes:
Conditions
Referenced to GND
Referenced to GND
Max of 10 seconds
-65
3.15
3.5
OE
OE
S1, S0
S1, S0
IOH=-12mA
IOL=12mA
IOH=-8mA
No Load
Each output
S1, S0, OE
All clocks
2
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5
0
DC CHARACTERISTICS (VDD = 3.3V unless noted)
AC CHARACTERISTICS (VDD = 3.3V unless noted)
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
10 kHz offset
0V
≤
VIN
≤
3.3V
40
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With an ICS/MicroClock approved pullable crystal.
3. To achieve this level of phase noise (lowest), REFCLK must be turned off by connecting REFEN to VDD.
3
Revision 082800
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
MDS 3732-15 A
PRELIMINARY INFORMATION
MK3732-15
Low Phase Noise VCXO+Multiplier
Package Outline and Package Dimensions
(
For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin TSSOP
Symbol
A
A1
b
c
D
E
E1
e
L
Millimeters
Min
Max
-
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
6.40 BSC
4.30
4.50
0.65 BSC
0.45
0.75
E1
E
INDEX
AREA
1
2
D
A1
e
b
c
A
L
Ordering Information
Part/Order Number
MK3732-15G
MK3732-15GTR
Revision history:
Version Revision
-
12139
A
8280
Comments
Original
Preliminary
Shipping packaging
tubes
tape and reel
Marking (both)
ICS (top line)
3732-15G (2nd line)
Package
16 pin TSSOP
16 pin TSSOP
Temperature
0-70 °C
0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
4
Revision 082800
Printed 11/16/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA •95126•(408) 295-9800tel• www.icst.com
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