EMBEDDED ULTRA-LOW POWER
Intel486
™
SX PROCESSOR
s
Ultra-Low Power Version of the Intel486™
s
176-Lead Thin Quad Flat Pack (TQFP)
SX Processor
s
— 32-Bit RISC Technology Core
s
— 8-Kbyte Write-Through Cache
s
— Four Internal Write Buffers
— Burst Bus Cycles
s
— Dynamic Bus Sizing for 8- and 16-bit
Data Bus Devices
— Intel System Management Mode (SMM)
— Boundary Scan (JTAG)
64-Bit Interunit Transfer Bus
32-Bit Data Bus
32-Bit Data Bus
Linear Address
32
32
32
PCD
PWT
Separate Voltage Supply for Core Circuitry
Fast Core-Clock Restart
Auto Clock Freeze
Ideal for Embedded Battery-Operated and
Hand-Held Applications
Core
Clock
Clock
Control
CLK Input
Barrel
Shifter
Register
File
ALU
Base/
Index
Bus
32
Segmentation
Unit
Descriptor
Registers
Limit and
Attribute PLA
2
Bus Interface
Paging
Unit
Cache Unit
20
32
Address
Drivers
Write Buffers
4 x 32
Data Bus
32
Transceivers
A31-A2
BE3#- BE0#
Physical
Address
Translation
Lookaside
Buffer
8 Kbyte
Cache
32
D31-D0
128
Bus Control
Displacement Bus
32
Prefetcher
Micro-
Instruction
32-Byte Code
Queue
2x16 Bytes
Request
Sequencer
ADS# W/R# D/C# M/IO#
PCD PWT RDY# LOCK#
PLOCK# BOFF# A20M#
BREQ HOLD HLDA
RESET SRESET INTR
NMI SMI# SMIACT#
STPCLK#
Control &
Protection
Test Unit
Code
Stream
Instruction
Decode
Decoded
Instruction
Path
24
Burst Bus
Control
BRDY# BLAST#
Control
ROM
Bus Size
Control
BS16# BS8#
Cache
Control
Boundary
Scan
Control
KEN# FLUSH#
AHOLD EADS#
TCK TMS
TDI TD0
A5850-01
Figure 1. Embedded Ultra-Low Power Intel486™ SX Processor Block Diagram
© INTEL CORPORATION, 1997
December 1997
Order Number:
272731-002
Information in this document is provided in connection with Intel products. No license, express or implied, by
estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in
Intel’s Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel
disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or
warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright
or other intellectual property right. Intel products are not intended for use in medical, life saving, or life
sustaining applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or
"undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them.
The Embedded Ultra-Low Power Intel486™ SX processor may contain design defects or errors known as
errata which may cause the product to deviate from published specifications. Current characterized errata are
available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your
product order.
Copies of documents which have an ordering number and are referenced in this document, or other Intel
literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
Copyright © Intel Corporation, 1997
*Third-party brands and names are the property of their respective owners.
Contents
Embedded Ultra-Low Power
Intel486
™
SX Processor
1.0 INTRODUCTION ........................................................................................................................................ 1
1.1 Features ............................................................................................................................................. 1
1.2 Family Members ................................................................................................................................. 2
2.0 HOW TO USE THIS DOCUMENT ............................................................................................................. 3
3.0 PIN DESCRIPTIONS ................................................................................................................................. 3
3.1 Pin Assignments ................................................................................................................................. 3
3.2 Pin Quick Reference ........................................................................................................................... 7
4.0 ARCHITECTURAL AND FUNCTIONAL OVERVIEW ............................................................................. 15
4.1 Separate Supply Voltages ................................................................................................................ 15
4.2 Fast Clock Restart ............................................................................................................................ 17
4.3 Level-Keeper Circuits ....................................................................................................................... 18
4.4 Low-Power Features ........................................................................................................................ 19
4.4.1 Auto Clock Freeze ................................................................................................................. 19
4.5 CPUID Instruction ............................................................................................................................. 19
4.5.1 Operation of the CPUID Instruction ....................................................................................... 19
4.6 Identification After Reset .................................................................................................................. 20
4.7 Boundary Scan (JTAG) .................................................................................................................... 21
4.7.1 Device Identification ............................................................................................................... 21
4.7.2 Boundary Scan Register Bits and Bit Order ........................................................................... 21
5.0 ELECTRICAL SPECIFICATIONS ........................................................................................................... 22
5.1 Maximum Ratings ............................................................................................................................. 22
5.2 DC Specifications ............................................................................................................................. 22
5.3 AC Specifications ............................................................................................................................. 25
5.4 Capacitive Derating Curves .............................................................................................................. 32
6.0 MECHANICAL DATA .............................................................................................................................. 33
6.1 Package Dimensions ........................................................................................................................ 33
6.2 Package Thermal Specifications ...................................................................................................... 34
FIGURES
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Embedded Ultra-Low Power Intel486™ SX Processor Block Diagram ...................................... i
Package Diagram for 176-Lead TQFP Package Embedded ULP Intel486™ SX Processor .... 4
Example of Supply Voltage Power Sequence ......................................................................... 16
Stop Clock State Diagram with Typical Power Consumption Values ...................................... 17
CLK Waveform ........................................................................................................................ 28
Input Setup and Hold Timing ................................................................................................... 28
Input Setup and Hold Timing ................................................................................................... 29
Output Valid Delay Timing ....................................................................................................... 29
Maximum Float Delay Timing .................................................................................................. 30
iii
Contents
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
TABLES
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
TCK Waveform ........................................................................................................................ 30
Test Signal Timing Diagram ..................................................................................................... 31
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a Low-to-High Transition ..................................................................................................... 32
Typical Loading Delay versus Load Capacitance under Worst-Case Conditions
for a High-to-Low Transition ..................................................................................................... 32
Package Mechanical Specifications for the 176 Lead TQFP Package .................................... 33
The Embedded Ultra-Low Power Intel486
™
SX Processor ....................................................... 2
Pin Assignment for 176-Lead TQFP Package Embedded ULP Intel486™ SX Processor ........ 5
Pin Cross Reference for 176-Lead TQFP Package Embedded ULP
Intel486™ SX Processor ............................................................................................................ 6
Embedded ULP Intel486™ SX Processor Pin Descriptions ...................................................... 7
Output Pins .............................................................................................................................. 12
Input/Output Pins ..................................................................................................................... 13
Test Pins .................................................................................................................................. 13
Input Pins ................................................................................................................................. 14
CPUID Instruction Description ................................................................................................. 19
Boundary Scan Component Identification Code ...................................................................... 21
Absolute Maximum Ratings ..................................................................................................... 22
Operating Supply Voltages ...................................................................................................... 22
DC Specifications ..................................................................................................................... 23
Active I
CC
Values ..................................................................................................................... 24
Clock Stop, Stop Grant, and Auto HALT Power Down I
CC
Values .......................................... 24
AC Characteristics ................................................................................................................... 25
AC Specifications for the Test Access Port ............................................................................. 27
Thermal Resistance ................................................................................................................. 34
Maximum Ambient Temperature (T
A
) ...................................................................................... 34
iv
Embedded Ultra-Low Power Intel486™ SX Processor
1.0
INTRODUCTION
This data sheet describes the embedded Ultra-Low
Power (ULP) Intel486™ SX processor. It is intended
for embedded battery-operated and hand-held appli-
cations. The embedded ULP Intel486 SX processor
provides all of the features of the Intel486 SX
processor except for the external data-bus parity
logic and the processor-upgrade pin. The processor
typically uses 20% to 50% less power than the
Intel486 SX processor. Additionally, the embedded
ULP Intel486 SX processor external data bus has
level-keeper circuitry and a fast-recovery core clock
which are vital for ultra-low-power system designs.
The processor is available in a Thin Quad Flat
Package (TQFP) enabling low-profile component
implementation.
The embedded ULP Intel486 SX processor consists
of a 32-bit integer processing unit, an on-chip cache,
and a memory management unit. The design
ensures full instruction-set compatibility with the
8086, 8088, 80186, 80286, Intel386™ SX, Intel386
DX, and all versions of Intel486 processors.
•
On-Chip Memory Management Unit
— Address
management and memory space protection
mechanisms maintain the integrity of memory in a
multitasking and virtual memory environment. Both
segmentation and paging are supported.
•
Burst Cycles
— Burst transfers allow a new
double word to be read from memory on each bus
clock cycle. This capability is especially useful for
instruction prefetch and for filling the internal
cache.
•
Write Buffers
— The processor contains four
write buffers to enhance the performance of
consecutive writes to memory. The processor can
continue internal operations after a write to these
buffers, without waiting for the write to be
completed on the external bus.
•
Bus Backoff
— When another bus master needs
control of the bus during a processor initiated bus
cycle, the embedded ULP Intel486 SX processor
floats its bus signals, then restarts the cycle when
the bus becomes available again.
•
Instruction Restart
— Programs can continue
execution following an exception generated by an
unsuccessful attempt to access memory. This
feature is important for supporting demand-paged
virtual memory applications.
•
Dynamic Bus Sizing
— External controllers can
dynamically alter the effective width of the data
bus. Bus widths of 8, 16, or 32 bits can be used.
•
Boundary Scan (JTAG)
— Boundary Scan
provides in-circuit testing of components on
printed circuit boards. The Intel Boundary Scan
implementation conforms with the IEEE Standard
Test Access Port and Boundary Scan Architecture.
•
Intel System Management Mode (SMM)
— A
unique Intel architecture operating mode provides
a dedicated special purpose interrupt and address
space that can be used to implement intelligent
power management and other enhanced functions
in a manner that is completely transparent to the
operating system and applications software.
•
I/O Restart
— An I/O instruction interrupted by a
System Management Interrupt (SMI#) can
automatically be restarted following the execution
of the RSM instruction.
•
Stop Clock
— The embedded ULP Intel486 SX
processor has a stop clock control mechanism that
provides two low-power states: a Stop Grant state
(40–85 mW typical, depending on input clock
frequency) and a Stop Clock state (~60 µW typical,
with input clock frequency of 0 MHz).
1.1
Features
The embedded ULP Intel486 SX processor offers
these features of the Intel486 SX processor:
•
32-bit RISC-Technology Core
— The embedded
ULP Intel486 SX processor performs a complete
set of arithmetic and logical operations on 8-, 16-,
and 32-bit data types using a full-width ALU and
eight general purpose registers.
•
Single Cycle Execution
— Many instructions
execute in a single clock cycle.
•
Instruction Pipelining
— Overlapped instruction
fetching, decoding, address translation and
execution.
•
On-Chip Cache with Cache Consistency
Support —
An 8-Kbyte, write-through, internal
cache is used for both data and instructions.
Cache hits provide zero wait-state access times
for data within the cache. Bus activity is tracked to
detect alterations in the memory represented by
the internal cache. The internal cache can be
invalidated or flushed so that an external cache
controller can maintain cache consistency.
•
External Cache Control
— Write-back and flush
controls for an external cache are provided so the
processor can maintain cache consistency.
1
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