PEX 8532AA/BA/BB
ExpressLane Versatile
PCI Express Switch
Data Book
Version 1.4
August 2006
Website
www.plxtech.com
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www.plxtech.com/support
Phone 408 774-9060
800 759-3735
FAX 408 774-2169
Copyright © 2006 by PLX Technology, Inc. All Rights Reserved – Version 1.4
August, 2006
Data Book
PLX Technology, Inc.
Copyright Information
Copyright © 2005 – 2006 PLX Technology, Inc. All rights reserved. The information in this document
is proprietary and confidential to PLX Technology No part of this document may be reproduced in any
form or by any means or used to make any derivative work (such as translation, transformation, or
adaptation) without written permission from PLX Technology.
PLX Technology provides this documentation without warranty, term or condition of any kind, either
express or implied, including, but not limited to, express and implied warranties of merchantability,
fitness for a particular purpose, and non-infringement. While the information contained herein is
believed to be accurate, such information is preliminary, and no representations or warranties of
accuracy or completeness are made. In no event will PLX Technology be liable for damages arising
directly or indirectly from any use of or reliance upon the information contained in this document.
PLX Technology may make improvements or changes in the product(s) and/or the program(s) described
in this documentation at any time.
PLX Technology retains the right to make changes to this product at any time, without notice. Products
may have minor variations to this publication, known as errata. PLX Technology assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology, Inc.
products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX
Technology, Inc.
PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG).
All product names are trademarks, registered trademarks, or service marks of their respective owners.
Order Number: 8532-SIL-DB-P1-1.4
ii
PEX 8532AA/BA/BB ExpressLane Versatile PCI Express Switch Data Book
Copyright © 2006 by PLX Technology, Inc. All Rights Reserved – Version 1.4
August, 2006
Revision History
Revision History
Version
Date
Description of Changes
Production Release, Silicon Revisions AA and BA.
Includes JTAG, power, and ordering information for Silicon Revision AA.
All information pertains to AA and BA devices, unless indicated otherwise
as PEX 8532AA or PEX 8532BA.
Chapter 9, “Hot Plug”: Removed watermark, and changed “8516” to “8532” in text.
•
•
•
•
•
•
•
•
1.2
February, 2006
•
•
•
•
•
Production Release, Silicon Revision BB, and updates to AA and BA
Changed EHBGA to Plastic BGA / PBGA
Corrected signal type listed for PEX_REFCLKn/p
Revised SerDes-related content to more specifically reference related lanes,
ports, and stations
Removed plural references to
upstream ports
Removed references to Promiscuous mode.
Section 8.2.2, “Port-to-Station
Aggregation”
– Corrected to indicate correct
combined port width for a single station
Section 12.1.2.2, “Intelligent
Adapter Mode NT Port Reset”
– Changed “1 ms”
to “1 µs” in second paragraph
Register 11-8, offset
1Ch[31]
– Corrected cross-reference to indicate the
Parity
Error Response Enable
bit
Register 11-49, offset
1CCh[13]
– Corrected value of 1 to indicate > 8
Corrected Table 17-1 title to indicate field value of 10b
Table A-1, “Serial EEPROM Memory Map”– Corrected addresses for Link Port
DF4h and DF8h offsets, and Virtual Port offsets DE0h through FDCh
Table A-1, “Serial EEPROM Memory Map”– Marked B80h - B88h, B98h, and
B9Ch as
Reserved,
and hyperlinked all register names in the “Register Name”
column to the register names in their respective chapters
Miscellaneous changes for readability
1.0
October, 2005
1.1
October, 2005
•
1.3
June, 2006
•
Figure 3-1 – Clarified view as “See-Through Top View”
•
Table 3-8 – Removed Hot Plug balls from N/C listing (J34, K34, L34, M34, N34,
P34, R34, T34, U34, V34, W34, Y34, AA34, AB34, AC34, AD34, AE34, AF34)
•
Section 5.1.3.1 – Changed “upstream and downstream stations” to “upstream and
downstream ports
”
•
Section 5.2.5, “Reset and Clock Initialization Timing” – Created new heading,
to include table and figure
•
Table 8-1 – Moved to “RAM and Queue Size” section
•
Figure 9-3 – Corrected HP_PERST# signal to be high
•
Chapter 11, register offset 1D0h – Changed “Reserved” reference
to “Factory
Test Only”
•
Section 12.4 – Changed “upstream port” reference to “downstream ports”
•
Chapters 15 and 16 – Changed “corresponding port” references to appropriate
NT Port interface
•
Section 17.1.7 – Removed reference to reserved registers for Station 1
•
Tables 17-3, 17-4, and 17-5 – Merged JTAG IDCODE content into a single table,
Table 17-3
•
Appendix B – Updated Product Ordering table
•
Miscellaneous changes for readability
PEX 8532AA/BA/BB ExpressLane Versatile PCI Express Switch Data Book
Copyright © 2006 by PLX Technology, Inc. All Rights Reserved – Version 1.4
iii
Data Book
PLX Technology, Inc.
Version
Date
Description of Changes
Miscellaneous changes and corrections. Major updates include the following:
•
Chapter 2 – Reorganized chapter
•
Sections 2.2.4, 4.5.2.1, 14.2.4 – Added information for dynamic port swapping
•
Global – Changed all “1.0V ±3%” references to “1.0V ±5%”
•
Global – Changed “TIC” to “Ingress”
•
Global – Added support for LVDS signaling
•
Global – Clarified port usage of the
Serial EEPROM Buffer
register (offset
264h)
•
Table 3-5 and Table 9-1, HP_BUTTON#, HP_MRL#, and HP_PRSNT# –
Added de-bounce footnote to Hot Plug signal tables
•
Table 3-5, HP_MRL# – Added note that if signal is enabled, it is not de-bounced
when sampled immediately after reset
•
Table 3-9, VSS_THERMAL – Removed “Not internally connected to the die”
•
Figure 4-7 – Replaced illustration
•
Section 6.2.1 – Revised content
•
Chapter 12 – Added new Figures 12-1 and 12-2, renumbered all other figures
•
Figure 14-1 – Added missing NT information
•
Chapter 17 – Clarified references to “Loop-Back TCB” bit [changed to “Physical
Layer Port Command
register
Port 0 or 8 Loop-Back
bit (offset
230h[0])”]
•
Chapters 17 and 18 – Moved “Thermal Characteristics” from Chapter 17
to Chapter 18
•
Chapter 18 – Revised with miscellaneous value changes and additions
Register updates:
•
Chapter 11 only
– Offsets
1D4h
and
1D8h
– Added new
Factory Test Only
registers,
Probe Select
and
Probe Output
– Offset
1DCh
– Changed “Only Port 0” in title to “Only Port 0, Except Bits
[29:28] Also Exist in NT Virtual and NT Link Interfaces”
– Offset
1DCh[15]
– Removed references to “mode select,” as this bit
does
not support
changing modes
– Offset
1DCh[29:28]
– Added Note regarding NT Configuration access
– Offset
1E4h
– Fields [31:24] and [15:8], changed port reference
from “all” to “0 and 8”
– Offset
224h
– Added Port Lane Width table
– Offset
668h
– Changed field name to “Ingress Port Enable” and added Port
Configuration (Lane Width) table
–
INCH Threshold Port Virtual Channel
registers, offsets
A00h, A18h, A30h,
A48h; A04h, A1Ch, A34h, A4Ch; A08h, A20h, A38h, A50h
– Added Payload,
Header, and Default values specific to Silicon Revisions BA and BB
– Offset
BE8h
– Added new register, Ingress One-Bit ECC Error Count
•
Chapters 11, 15, and 16
–
Revision ID
(offset
08h)
– Added note that bit 0 is hardwired to 1 for Silicon
Revision BB
–
PCI Express Capabilities
registers – Changed to include
reserved
offsets 84h through 8Ch
– Offset
668h
– Removed “Factory Test Only” from register name
•
Chapters 11 and 16 – Changed offsets
BECh
and
BFCh
to “Only Port 0”
•
Chapter 15 only
– Added reserved Expansion ROM register at offset
30h
– Offsets
D6Ch
through
D90h
– Significantly revised registers
•
Chapters 15 and 16
– Offsets
D0h
through
F4h, C3Ch
through
C58h
– Significantly revised registers
– Debug Register Map – Added information related to
Debug Control
register,
offset 1DCh[29:28]
Table A-1, “Serial EEPROM Memory Map”
•
Corrected serial EEPROM address entries
•
Added register entries for new registers at
1D4h, 1D8h,
and
BE8h.
1.4
August, 2006
iv
PEX 8532AA/BA/BB ExpressLane Versatile PCI Express Switch Data Book
Copyright © 2006 by PLX Technology, Inc. All Rights Reserved – Version 1.4
August, 2006
Preface
Preface
The information contained in this document is subject to change without notice. This PLX document to
be updated periodically as new information is made available.
This data book documents information for the PEX 8532, Silicon Revisions AA, BA, and BB. The
information provided pertains to all silicon revisions, unless specified otherwise as PEX 8532AA,
PEX 8532BA, or PEX 8532BB.
Audience
This data book provides the functional details of the PLX Technology ExpressLane
TM
PEX 8532
Versatile PCI Express Switch, for hardware designers and software/firmware engineers.
Supplemental Documentation
This data book assumes that the reader is familiar with the following documents:
•
PCI Special Interest Group (PCI-SIG)
3855 SW 153rd Drive, Beaverton, OR 97006 USA
Tel: 503 619-0569, Fax: 503 644-6708,
http://www.pcisig.com
– PCI Local Bus Specification, Revision 2.3
– PCI Bus Power Management Interface Specification, Revision 1.1
– PCI to PCI Bridge Architecture Specification, Revision 1.1
– PCI Hot Plug Specification, Revision 1.1
– PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0
– PCI Express Base Specification 1.0a
– PCI Express Card Electromechanical Specification, Revision 1.0a
•
The Institute of Electrical and Electronics Engineers, Inc.
445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA
Tel: 800 678-4333 (domestic only) or 732 981-0060, Fax: 732 981-1721,
http://www.ieee.org
– IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan
Architecture, 1990
– IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture
– IEEE Standard 1149.1-1994, Specifications for Vendor-Specific Extensions
– IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan
Architecture Extensions
PEX 8532AA/BA/BB ExpressLane Versatile PCI Express Switch Data Book
Copyright © 2006 by PLX Technology, Inc. All Rights Reserved – Version 1.4
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