PEX 8524
Versatile PCI Express Switch
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Version 0.99
June 2005
Website
www.plxtech.com
Phone 408 774-9060
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PLX Technology Confidential
-
Version 0.99
June, 2005
Data Book
Data Book
PLX Technology, Inc.
Revision History
Preface
The information contained in this document is subject to change without notice. This PLX Document to
be updated periodically as new information is made available.
Audience
This data book provides the functional details of the PLX Technology
PEX 8524
Versatile PCI Express
Switch, for both hardware designers and software/firmware engineers.
Supplemental Documentation
This data book assumes that the reader is familiar with the documents referenced below.
•
PCI Special Interest Group (PCI-SIG)
5440 SW Westgate Drive #217, Portland, OR 97221 USA
– PCI Local Bus Specification, Revision 2.3
– PCI Express Base Specification 1.0a
– PCI Bus Power Management Interface Specification, Revision 1.1
– PCI Express Card Electromechanical Specification, Revision 1.0a
– PCI Hot Plug Specification, Revision 1.1
– PCI Standard Hot Plug Controller and Subsystem Specification, Revision 1.0
•
The Institute of Electrical and Electronics Engineers, Inc.
445 Hoes Lane, PO Box 1331, Piscataway, NJ 08855-1331, USA
Tel: 800 678-4333 (domestic only) or 732 981-0060, Fax: 732 981-1721,
http://www.ieee.org
– IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan
Architecture, 1990
– IEEE 1149.1a-1993, IEEE Standard Test Access Port and Boundary-Scan Architecture
– IEEE Standard 1149.1b-1994, Specifications for Vendor-Specific Extensions
– IEEE Standard 1149.6-2003, IEEE Standard Test Access Port and Boundary-Scan
Architecture Extensions
Note:
In this data book, shortened titles are provided to the previously listed documents.
The following table lists these abbreviations.
Abbreviation
PCI r2.3
PCI Express Base 1.0a
PCI Power Mgmt. r1.1
PCI ExpressCard 1.0a
PCI HotPlug 1.1
PCI Standard Hot Plug r1.0
IEEE Standard 1149.1-1990
Document
PCI Local Bus Specification, Revision 2.3
PCI Express Base Specification 1.0a
PCI Bus Power Management Interface Specification, Revision 1.1
PCI Express Card Electromechanical Specification, Revision 1.0a
PCI Hot Plug Specification, Revision 1.1
PCI Standard Hot Plug Controller and Subsystem Specification,
Revision 1.0
IEEE Standard Test Access Port and Boundary-Scan Architecture
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Tel: 503 291-2569, Fax: 503 297-1090,
http://www.pcisig.com
PEX 8524 Versatile PCI Express™ Switches Data Book
Copyright © 2005 by PLX Technology, Inc. All Rights Reserved
–
Version 0.99 Confidential
June, 2005
PLX Technology, Inc.
Terms and Abbreviations
The following table lists common terms and abbreviations used in this document. Terms and
abbreviations defined in the
PCI Express Base 1.0a
are not included in this table.
Terms and Abbreviations
Terms and
Abbreviations
AMCAM
Definitions
Address mapping CAM that determines a memory request route. It contains mirror copies of
the PCI-to-PCI Bridges Memory Base and Limit registers in the switch.
Bus Number mapping CAM that determines the completion route. It contains mirror copies
of the PCI-to-PCI Bridges Secondary Bus-Number and Subordinate Bus-Number registers in
the switch.
Content Addressable Memory.
Configuration Space registers.
BusNoCAM
CAM
CSRs
Downstream
Station
Egress Q
Foreign
Ingress Q
IOAMCAM
Lane
Local
Copyright Information
Copyright © 2003, 2004, 2005 PLX Technology, Inc. All rights reserved. The information in this
document is proprietary and confidential to PLX Technology, Inc. No part of this document may be
reproduced in any form or by any means or used to make any derivative work (such as translation,
transformation, or adaptation) without written permission from PLX Technology.
PLX Technology provides this documentation without warranty, term or condition of any kind, either
express or implied, including, but not limited to, express and implied warranties of merchantability,
fitness for a particular purpose, and non-infringement. While the information contained herein is
believed to be accurate, such information is preliminary, and no representations or warranties of
accuracy or completeness are made. In no event will PLX Technology be liable for damages arising
directly or indirectly from any use of or reliance upon the information contained in this document.
PLX Technology may make improvements or changes in the product(s) and/or the program(s) described
in this documentation at any time.
PLX Technology retains the right to make changes to this product at any time, without notice. Products
may have minor variations to this publication, known as errata. PLX Technology assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology,
Inc. products.
PLX Technology, the PLX logo, and Data Pipe Architecture are registered trademarks of PLX
Technology, Inc. PCI Express is a trademark of the PCI Special Interest Group.
All product names are trademarks, registered trademarks, or service marks of their respective owners.
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A station that contains only Downstream ports.
•
Egress – Outgoing traffic from chip.
•
Egress Q – Egress queuing/scheduling mechanism.
•
Ingress – Incoming traffic to chip.
•
Ingress Q – Ingress queuing/scheduling mechanism.
Reference to PCI Express attributes that belong to (off-chip) PCI Express components
located on the other side of PCI Express links.
I/O Address mapping CAM that determines an I/O request route. It contains mirror copies of
the PCI-to-PCI Bridges I/O Base and Limit registers in the switch.
Lanes are comprised of a bi-directional pair of differential PCI Express I/O signals.
Reference to PCI Express attributes (such
as,
credits) that belong to the PCI Express station.
PEX 8524 Versatile PCI Express™ Switches Data Book
Copyright © 2005 by PLX Technology, Inc. All Rights Reserved
–
Version 0.99 Confidential
Data Book
PLX Technology, Inc.
Terms and Abbreviations
(Cont.)
Terms and
Abbreviations
Non-Transparent
PCI Express
Station
PHY
Port
QoS
RAS
RR
SerDes
TC
TDM
TLC
TLP
Definitions
A bridging technique used in the PCI Express Switch to isolate memory spaces by presenting
the processor as an endpoint rather than another memory system.
A functional unit that provides the PCI Express conforming system interface. It includes the
Serializer and De-serializer (SerDes) hardware interface modules and PCI Express Interface,
which provides the Physical Layer, Data Link Layer, and Transaction Layer logic.
Physical Layer.
Ports are a collection of lanes configured at startup which contain the functional logic and
memory resources to communicate with like resources in other PCI Express devices.
Quality of Service.
Reliability, Availability, and Serviceability.
Round-Robin scheduling.
Transparent
Upstream station
VC
WRR
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Traffic Class.
Time Division Multiplexing.
Virtual Channel.
Weighted Round-Robin scheduling.
Serializer/De-serializer. A high-speed differential-signaling parallel-to-serial and serial-to-
parallel conversion logic attached to lane pads.
Transaction Layer Control. The module performing PCI Express Transaction Layer
functions.
Transaction Layer Packet. PCI-Express packet formation and organization.
Refers to standard PCI Express upstream-to-downstream routing protocol.
Upstream station. Contains the component’s Upstream port. An upstream station may contain
Downstream ports.
PEX 8524 Versatile PCI Express™ Switches Data Book
Copyright © 2005 by PLX Technology, Inc. All Rights Reserved
–
Version 0.99 Confidential
June, 2005
Register Types
Register Types
The following table describes the
PEX 8524
register types, grouped by accessibility.
Register Types
Type
HwInit
R/W
R/W1C
Description
Hardware Initialized Register or Bit.
Refers to the
PEX 8524
hardware initialization
mechanism or
PEX 8524
EEPROM register initialization feature. Read-Only after
initialization and can only be reset with Fundamental Reset.
Read-Write Register.
Read/write and is set or cleared to the desired state by software.
Read-Only Status.
Write “1b” to clear Status register or bit. Indicate status when read.
A status bit set by the system to “1b” (to indicate status) is cleared by writing a “1b” to
that bit. Writing “0b” has no effect.
Read-Only Status.
Write “1b” to clear status register or bit. Indicate status when read.
A status bit set by the system to “1b” to indicate status is cleared by writing a “1b” to
that bit. Writing “0b” does not have an effect. Bits are not initialized or modified by
Hot Reset.
R/W1CS
PEX 8524 Versatile PCI Express™ Switches Data Book
Copyright © 2005 by PLX Technology, Inc. All Rights Reserved
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Version 0.99 Confidential
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R/W1S
R/WS
RO
ROS
Write “1b” to Set Register.
Non-transparent ports contain these types of
Device-Specific Control registers. Software writes “1b” to the register to enable control
and “1b” to a register with R/W1C privilege to clear the control. Writing “0b” has
no effect.
Read-Write Register or Bit.
Read/write and is set or cleared to the desired state by
software. Bits are not initialized or modified by Hot Reset.
Read-Only register.
Read-Only and cannot be altered by software. Initialized by the
PEX 8524
hardware initialization mechanism or
PEX 8524
EEPROM register
initialization feature.
Read-Only Sticky.
Read-Only and cannot be altered by software. Initialized by the
PEX 8524
hardware initialization mechanism or
PEX 8524
EEPROM register
initialization feature. Bits are not initialized or modified by Hot Reset.
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