电子工程世界电子工程世界电子工程世界

关键词

搜索

型号

搜索

PEX8518-AA25BIG

产品描述PEX8518-AA25BIG
产品类别嵌入式处理器和控制器    微控制器和处理器   
文件大小263KB,共4页
制造商AVAGO
官网地址http://www.avagotech.com/
下载文档 详细参数 选型对比 全文预览

PEX8518-AA25BIG概述

PEX8518-AA25BIG

PEX8518-AA25BIG规格参数

参数名称属性值
厂商名称AVAGO
包装说明,
Reach Compliance Codecompliant

文档预览

下载PDF文档
Version 1.2 2006
PEX 8518
Features
PEX 8518 General Features
o
16-lane PCI Express switch
-
Integrated SerDes
o
Up to five configurable ports
o
23mmx23mm, 376-ball PBGA package
o
Maximum Power: 3.53 Watts
PEX 8518 Key Features
o
Standards Compliant
-
PCI Express Base Specification, r1.1
o
High Performance
-
Non-blocking switch fabric
-
Full line rate on all ports
-
Packet Cut-Thru with 150ns max
packet latency (x4 to x4)
o
Non-Transparent Bridging
-
Configurable Non-Transparent port
for Multi-Host or Intelligent I/O
Support
o
Flexible Configuration
-
Five highly flexible & configurable
ports (x1, x2, x4, or x8)
-
Configurable with strapping pins,
EEPROM, I
2
C, or Host software
-
Lane and polarity reversal
o
PCI Express Power Management
-
Link power management states: L0,
L0s, L1, L2/L3 Ready, and L3
-
Device states: D0 and D3hot
o
Quality of Service (QoS)
-
Two Virtual Channels per port
-
Eight Traffic Classes per port
-
Fixed and Round-Robin Virtual
Channel Port Arbitration
o
Reliability, Availability, Serviceability
-
5 Standard Hot-Plug Controllers
-
Upstream port as hot-plug client
-
Transaction Layer end-to-end CRC
-
Poison bit
-
Advanced Error Reporting
-
Lane Status bits and GPO available
-
Per port error diagnostics
Bad DLLPs
Bad TLPs
CRC errors
-
JTAG boundary scan
Flexible & Versatile PCI Express Switch
Multi-purpose, Feature Rich
ExpressLane™
PCI Express Switch
The
ExpressLane
PEX 8518 device offers PCI Express switching capability
enabling users to add scalable high bandwidth, non-blocking interconnection
to a wide variety of applications including
servers, storage systems,
communications platforms, blade servers, and embedded-control
products.
The PEX 8518 is well suited for
fan-out, aggregation, peer-to-
peer,
and
intelligent I/O module
applications.
Highly Flexible Port Configurations
The PEX 8518 offers highly configurable ports. There are a maximum of 5
ports that can be configured to any legal width from x1 to x8, in any
combination to support your specific bandwidth needs. The ports can be
configured for
symmetric
(each port having the same lane width and traffic
load) or
asymmetric
(ports having different lane widths) traffic. In the event
of asymmetric traffic, the PEX 8518 features a
flexible central packet
memory
that allocates a memory buffer for each port as required by the
application or endpoint. This buffer allocation along with the device's
flexible packet flow control
minimizes bottlenecks when the upstream and
aggregated downstream bandwidths do not match (are asymmetric). Any of
the ports can be designated as the upstream port, which can be changed
dynamically.
End-to-end Packet Integrity
The PEX 8518 provides
end-to-end CRC
protection (ECRC) and
Poison
bit
support to enable designs that require
guaranteed error-free packets.
These
features are optional in the PCI Express specification, but PLX provides
them across its entire
ExpressLane
switch product line.
Non-Transparent “Bridging” in a PCI Express Switch
The PEX 8518 product supports full non-transparent bridging (NTB)
functionality to allow implementation of
multi-host systems
and
intelligent
I/O modules
in applications such as
communications, storage,
and
blade
servers.
To ensure quick product migration, the non-transparency features
are implemented in the same fashion as in standard PCI applications.
Non-transparent bridges allow systems to isolate memory domains by
presenting the processor subsystem as an endpoint, rather than another
memory system. Base address registers are used to translate addresses;
doorbell registers are used to send interrupts between the address domains;
and scratchpad registers are accessible from both address domains to allow
inter-processor communication.
Two Virtual Channels
The
ExpressLane
PEX 8518 switch supports 2 full-featured Virtual Channels
(VCs) and a full 8 Traffic Classes (TCs). The mapping of Traffic Classes to
port-specific Virtual Channels allows for different mappings for different
ports. In addition, the devices offer user-selectable Virtual Channel
arbitration algorithms to enable users to fine tune the Quality of Service
(QoS) required for a specific application.

PEX8518-AA25BIG相似产品对比

PEX8518-AA25BIG PEX8518-AA25BI
描述 PEX8518-AA25BIG PEX8518-AA25BI
厂商名称 AVAGO AVAGO
Reach Compliance Code compliant compliant

 
EEWorld订阅号

 
EEWorld服务号

 
汽车开发圈

 
机器人开发圈

About Us 关于我们 客户服务 联系方式 器件索引 网站地图 最新更新 手机版

站点相关: 大学堂 TI培训 Datasheet 电子工程 索引文件: 1236  506  457  407  2912  51  56  21  35  12 

器件索引   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

北京市海淀区中关村大街18号B座15层1530室 电话:(010)82350740 邮编:100190

电子工程世界版权所有 京B2-20211791 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号 Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved