Data Book
PLX Technology, Inc.
Copyright Information
Copyright © 2006 –2007 PLX Technology, Inc. All rights reserved. The information in this document is
proprietary and confidential to PLX Technology No part of this document may be reproduced in any
form or by any means or used to make any derivative work (such as translation, transformation, or
adaptation) without written permission from PLX Technology.
PLX Technology provides this documentation without warranty, term or condition of any kind, either
express or implied, including, but not limited to, express and implied warranties of merchantability,
fitness for a particular purpose, and non-infringement. While the information contained herein is
believed to be accurate, such information is preliminary, and no representations or warranties of
accuracy or completeness are made. In no event will PLX Technology be liable for damages arising
directly or indirectly from any use of or reliance upon the information contained in this document.
PLX Technology may make improvements or changes in the product(s) and/or the program(s) described
in this documentation at any time.
PLX Technology retains the right to make changes to this product at any time, without notice. Products
may have minor variations to this publication, known as errata. PLX Technology assumes no liability
whatsoever, including infringement of any patent or copyright, for sale and use of PLX Technology, Inc.
products.
PLX Technology and the PLX logo are registered trademarks and ExpressLane is a trademark of PLX
Technology, Inc.
PCI Express is a trademark of the PCI Special Interest Group (PCI-SIG).
All product names are trademarks, registered trademarks, or service marks of their respective owners.
Order Number: 8516-SIL-DB-P1-1.4
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PEX 8516AA/BA/BB ExpressLane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.4
January, 2007
Revision History
Revision History
Version
Date
Description of Changes
Production Release, Silicon Revisions AA and BA.
Includes JTAG, power, and ordering information for Silicon Revision AA.
All information pertains to AA and BA devices, unless indicated otherwise
as PEX 8516AA or PEX 8516BA.
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1.1
February, 2006
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Production Release, Silicon Revision BB, and updates to AA and BA
Changed EHBGA to Plastic BGA / PBGA
Corrected signal type listed for PEX_REFCLKn/p
Revised SerDes-related content to more specifically reference related lanes
Removed references to
downstream station
Removed plural references to
upstream ports
Removed references to non-existent STRAP_PROM# ball
Register 11-51, “1DCh,
Debug Control”
– Removed Promiscuous mode references
Table 5-2 – Corrected
reserved
range for LOAD_UPSTREAM_PORT_ID[11:8]
values
Section 12.1.2.2, “Intelligent
Adapter Mode NT Port Reset”
– Changed “1 ms”
to “1 µs” in second paragraph
Register 11-8, offset
1Ch[31]
– Corrected cross-reference to indicate the
Parity
Error Response Enable
bit
Register 11-49, offset
1CCh[13]
– Corrected value of 1 to indicate > 8
Register 11-57, “1F4h,
Software-Controlled Lane Status”
– Corrected to indicate
correct number of lanes
Corrected Table 17-1 title to indicate field value of 10b
Table A-1, “Serial EEPROM Memory Map”– Corrected addresses for Link Port
DF4h and DF8h offsets, and Virtual Port offsets DE0h through FDCh
Miscellaneous changes for readability
1.0
October, 2005
1.2
June, 2006
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Figure 3-1 – Clarified view as “See-Through Top View”
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Section 5.1.3.1 – Changed “upstream station” to “upstream and downstream ports
”
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Section 5.2.5, “Reset and Clock Initialization Timing” – Created new heading,
to include table and figure
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Table 8-1 – Moved to “RAM and Queue Size” section
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Figure 9-3 – Corrected HP_PERST# signal to be high
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Chapter 11, register offset 1D0h – Changed “Reserved” reference
to “Factory
Test Only”
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Section 12.4 – Changed “upstream port” reference to “downstream ports”
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Chapters 15 and 16 – Changed “corresponding port” references to appropriate
NT Port interface
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Section 17.1.7 – Removed reference to Station 1
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Tables 17-3, 17-4, and 17-5 – Merged JTAG IDCODE content into a single table,
Table 17-3
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Appendix B – Updated Product Ordering table
•
Miscellaneous changes for readability
PEX 8516AA/BA/BB ExpressLane Versatile PCI Express Switch Data Book
Copyright © 2007 by PLX Technology, Inc. All Rights Reserved – Version 1.4
iii
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