UVEPROM
Austin Semiconductor, Inc.
256K UVEPROM
UV Erasable Programmable
Read-Only Memory
AVAILABLE AS MILITARY
SPECIFICATIONS
• -55C to 125C operation
• MILITARY Processing Methods
• Commercial Version Available
AS27C256A
PIN ASSIGNMENT
(Top View)
28-Pin DIP (J)
(600 MIL)
V
PP
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A14
A13
A8
A9
A11
G\
A10
E\
DQ7
DQ6
DQ5
DQ4
DQ3
FEATURES
Organized 32,768 x 8
Single +5V ±10% power supply
Pin-compatible with existing 256K ROM’s and EPROM’s
All inputs/outputs fully TTL compatible
Power-saving CMOS technology
Very high-speed FLASHRITE Pulse Programming
3-state output buffers
400-mV DC assured noise immunity with standard TTL
loads
• Latchup immunity of 250 mA on all input and output pins
• Low power dissipation (CMOS Input Levels)
-Active - 165mW Worst Case
-Standby - 1.7mW Worst Case (CMOS-input levels)
* FUTURE High Speed Offerings: 55ns, 70ns, 90ns
•
•
•
•
•
•
•
•
32-Pin LCC (ECA)
(450 x 550 mils)
A7
A12
A12
A14
6
A10
V
PP
NC
NC
V
CC
V
CC
A15
A14
CE2
A13
4 3 2 1 32 31 30
OPTIONS
• Timing
120ns access
150ns access
170ns access
200ns access
250ns access
MARKING
-12
-15
-17
-20
-25
A6
5
A7
A5
6
A6
A4
7
A5
A3
8
A4
A2
9
A3
A2 10
A1
A1 11
A0
A0 12
NC
DQ1 13
DQ0
29
A8
\
WE
28
A9
A13
27
A11
A8
26
NC
A9
25
G\
A11
24
A10
\
OE
23
E\
A10
22
DQ7
\
CE1
21
DQ6
DQ8
14 15 16 17 18 19 20
• Package(s)
Ceramic DIP (600mils)
J
No. 110
Ceramic LCC (450 x 550 mils) ECA No. 208
• Operating Temperature Ranges
Military (-55
o
C to +125
o
C)
M
Industrial (-40°C to +85°C)
I
• Processing Ranges
Military 883 Non-Compliant Equivalent /MIL
Commercial
blank
Pin Name
A0 - A14
DQ0-DQ7
E\
G\
GND
V
CC
V
PP
Function
Address Inputs
Inputs (programming)/Outputs
Chip Enable/Power Down
Output Enable
Ground
5V Supply
13V Programming Power Supply
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS27C256A
Rev. 1.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
DQ1
DQ2
DQ2
DQ3
V
SS
GND
DQ4
NC
DQ5
DQ3
DQ6
DQ4
DQ7
DQ5
UVEPROM
Austin Semiconductor, Inc.
GENERAL DESCRIPTION
The AS27C256A series is a set of 262,144 bit, ultraviolet-
light erasable, electrically programmable read-only
memo-
ries. These devices are fabricated using power-saving CMOS
technology for high speed and simple interface with MOS and
bipolar circuits. All inputs (including program data inputs)
can be driven by Series 54 TTL circuits without the use of
external pullup resistors. Each output can drive one Series 54
TTL circuit without external resistors. The data outputs are 3-
state for connecting multiple devices to a common bus. The
AS27C256A is pin-compatible with 28-pin 256K ROMs and
EPROMs. It is offered in a 600mil dual-in-line ceramic pack-
age (J suffix) and a 450 x 550 mil ceramic LCC (ECA suffix)
rated for operation from -55°C to 125°C.
Because this EPROM operates from a single 5V supply (in
the read mode), it is ideal for use in microprocessor-based sys-
tems. One other supply (12.75V) is needed for programming.
All programming signals are TTL level. This device is
programmable by the AMD FLASHRITE Pulse programming
algorithm. The FLASHRITE Pulse programming algorithm
uses a V
PP
of 12.75VV and a V
CC
of 6.25V for a nominal pro-
gramming time of four seconds. For programming outside the
system, existing EPROM programmers can be used. Loca-
tions can be
programmed singly, in blocks, or at random.
AS27C256A
FUNCTIONAL BLOCK DIAGRAM*
EPROM 32,768 x 8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
E\
G\
10
9
8
7
6
5
4
3
25
24
21
23
2
26
27
20
22
0
A
0
32,767
A
A
A
A
A
A
A
A
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
14
[PWR DWN]
&
EN
* This symbol is in accordance with ANSI/IEEE std 91-1984 and IEC Publication 617-12.
AS27C256A
Rev. 1.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
UVEPROM
Austin Semiconductor, Inc.
READ/OUTPUT DISABLE
When the outputs of two or more AS27C256A are connected
in parallel on the same bus, the output of any particular device
in the circuit can be read with no interference from the com-
peting outputs of the other devices. To read the output of the
selected AS27C256A, a low-level signal is applied to E\ and
G\. All other devices in the circuit should have their outputs
disabled by applying a high-level signal to one of these pins.
Output data is accessed at pins DQ0 through DQ7.
AS27C256A
FLASHRITE PULSE PROGRAMMING
The AS27C256A EPROM is programmed by using the AMD
FLASHRITE Pulse programming algorithm as illustrated by
the flowchart in Figure 1. This algorithm programs the device
in a nominal time of 4 seconds. Actual programming time
varies as a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7.
Once addresses and data are stable, E\ is pulsed.
The FLASHRITE Pulse programming algorithm uses initial
pulses of 100 microseconds (µs) followed by a byte-verifica-
tion step to determine when the addressed byte has been suc-
cessfully programmed. Up to 25 100µs pulses per byte are
provided before a failure is recognized.
The programming mode is achieved when V
PP
= 12.75V,
V
CC
= 6.25V, G\ = V
IH
, and E\ = V
IL
. More than one device can
be programmed when the devices are connected in parallel.
Locations can be programmed in any order. When the AMD
FLASHRITE Pulse programming routine is completed, all bits
are verified with V
CC
= V
PP
= 5V.
LATCHUP IMMUNITY
Latchup immunity on the AS27C256A is a minimum of 250mA
on all inputs and outputs. This feature provides latchup
im-
munity beyond any potential transients at the printed
cir-
cuit board level when the EPROM is interfaced to industry
standard TTL or MOS logic devices. Input/output layout
approach controls latchup without compromising performance
or packing density.
POWER DOWN
Active I
CC
supply current can be reduced from 25mA
(AS27C256A-12 through AS27C256A-25) to 1mA (TTL-level
inputs) or 300µA (CMOS-level inputs) by applying a high TTL/
CMOS signal to the E\ pin. In this mode all outputs are in the
high-impedance state.
PROGRAM INHIBIT
Programming can be inhibited by maintaining a high-level
input on E\.
ERASURE
Before programming, the AS27C256A is erased by exposing
the chip through the transparent lid to a high-intensity ultra-
violet light (wavelength 2537 Å). EPROM erasure before pro-
gramming is necessary to ensure that all bits are in the logic-
high state. Logic-lows are programmed into the desired loca-
tions. A programmed logic-low can be erased only by ultra-
violet light. The recommended minimum exposure dose (UV
intensity x exposure time) is 15W•s/cm
2
. A typical 12mW/
cm
2
, filterless UV lamp erases the device in 21 minutes. The
lamp should be located about 2.5cm above the chip during
erasure. After erasure, all bits are in the high state. It should
be noted that normal ambient light contains the correct wave-
length for erasure; therefore, when using the AS27C256A, the
window should be covered with an opaque label.
PROGRAM VERIFY
Programmed bits can be verified with V
PP
= 12.75V when G\
= V
IL
, and E\ = V
IH
.
SIGNATURE MODE
The signature mode provides access to a binary code
identifying the manufacturer and device type. This mode is
activated when A9 is forced to 12V ±0.5V. Two identifier bytes
are accessed by A0 (terminal 10); i.e., A0=V
IL
accesses the
manufacturer code, which is output on DQ0-DQ7; A0=V
IH
accesses the device code, which is also output on DQ0-DQ7.
All other addresses must be held at VIL. Each byte contains
odd parity on bit DQ7. The manufacturer code for these de-
vices is 01h and the device code is 10h.
AS27C256A
Rev. 1.1 6/05
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
模拟与混合信号
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
