September 2006
H Y S6 4D 12 8021 [ E/ H ] B DL – 5 – C
H Y S6 4D 12 8021 [ E/ H ] B DL – 6 – C
200-Pin-Small-Outline Double-Data-Rate SDRAM
SO-DIMM
DDR SDRAM
RoHS Compliant Products
Internet Data Sheet
Rev. 1.11
Internet Data Sheet
HYS64D128021[E/H]BDL–[5/6]–C
Small-Outline DDR SDRAM Modules
HYS64D128021[E/H]BDL–5–C, HYS64D128021[E/H]BDL–6–C
Revision History: 2006-09, Rev. 1.11
Page
All
All
20
Subjects (major changes since last revision)
Qimonda update
Adapted internet edition
changed
t
RFC
for DDR400 from 70 ns to 65 ns
Previous Revision: 2006-01, Rev. 1.10
Previous Revision: 2005-04, Rev. 1.0
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09152006-CQZM-KWJ4
2
Internet Data Sheet
HYS64D128021[E/H]BDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1
Overview
This chapter gives an overview of the 200-Pin-Small-Outline Double-Data-Rate SDRAM product family and describes its main
characteristics.
1.1
Features
• 200-Pin-Small-Outline Double-Data-Rate SDRAM for PC and Workstation main memory applications
• Two ranks 128M
×64
organization
• JEDEC standard Double Data Rate Synchronous DRAMs (DDR SDRAM) Single +2.5V (±0.2V) and +2.6V (±0.1V) power
supply for DDR400
• Built with 512 Mbit DDR SDRAM in P-FBGA-60 package
• Programmable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave)
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_2 compatible
• Serial Presence Detect with E
2
PROM
• Standard MO-206 form factor: 133.35 mm
×
31.75 mm
×
3.80 mm max.
• Standard reference layout
• Gold plated contacts
• RoHS compliant product
1)
TABLE 1
Performance for –5 and –6
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
@CL3
@CL2.5
@CL2
–5
DDR400B
–6
DDR333B
166
166
133
Unit
—
MHz
MHz
MHz
f
CK3
f
CK2.5
f
CK2
200
166
133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.11, 2006-09
09152006-CQZM-KWJ4
3
Internet Data Sheet
HYS64D128021[E/H]BDL–[5/6]–C
Small-Outline DDR SDRAM Modules
1.2
Description
(SPD) based on a serial E
2
PROM device using the 2-pin I
2
C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer
The
Qimonda
HYS64D128021[E/H]BDL–5–C,
HYS64D128021[E/H]BDL–6–C and are industry standard
200-Pin-Small-Outline Double-Data-Rate SDRAM (SO-
DIMM) organized as 128M
×
64 for non-parity memory
applications. The memory array is designed with 512-Mbit
Double-Data-Rate Synchronous DRAMs. A variety of
decoupling capacitors are mounted on the printed
circuit board. The DIMMs feature serial presence detect
TABLE 2
Ordering Information for Lead-Free Products (RoHS Compliant Product)
Product Type
1)
PC3200 (CL=3.0)
HYS64D128021EBDL–5–C
3)
PC2700 (CL=2.5)
HYS64D128021EBDL–6–C
PC2700S–2533–1–Z
2 Ranks 1 GB DIMM
512 Mbit (×8)
1) All product types end with a place code designating the silicon-die revision. Reference information available on request. Example:
HYS64D128021HBDL-5-C, indicating Rev.C die are used for SDRAM components.
2) The Compliance Code is printed on the module labels and describes the speed sort (for example “PC3200”), the latencies (for example
“30330” means CAS latency of 3.0 clocks, Row-Column-Delay (RCD) latency of 3 clocks and Row Precharge latency of 3 clocks), JEDEC
SPD code definition version 0, and the Raw Card used for this module.
3) EBDL: Halogen free
Compliance Code
2)
PC3200S–3033–1–Z
Description
2 Ranks 1 GB DIMM
SDRAM Technology
512 Mbit (×8)
Rev. 1.11, 2006-09
09152006-CQZM-KWJ4
4
Internet Data Sheet
HYS64D128021[E/H]BDL–[5/6]–C
Small-Outline DDR SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered Small Outline DDR SDRAM DIMM is listed by function in
Table 3
(200 pins). The
abbreviations used in columns Pin and Buffer Type are explained in
Table 4
and
Table 5
respectively. The pin numbering is
depicted in
Figure 1.
TABLE 3
Pin Configuration of SO-DIMM
Pin#
Clock Signals
35
160
89
37
158
91
96
95
CK0
CK1
CK2
NC
CK0
CK1
CK2
NC
CKE0
CKE1
NC
Control Signals
121
122
S0
S1
NC
118
120
119
RAS
CAS
WE
I
I
NC
I
I
I
SSTL
SSTL
–
SSTL
SSTL
SSTL
Chip Select Rank 0
Chip Select Rank 1
Note: 2-ranks module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
I
I
I
NC
I
I
I
NC
I
I
NC
SSTL
SSTL
SSTL
–
SSTL
SSTL
SSTL
–
SSTL
SSTL
–
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
Complement Clock
Complement Clock
Complement Clock
Clock Signal
Clock Signal
Clock Signal
Name
Pin
Type
Buffer
Type
Function
Rev. 1.11, 2006-09
09152006-CQZM-KWJ4
5