HY27US(08/16)121A Series
HY27SS(08/16)121A Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Document Title
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash Memory
Revision History
Revision
No.
0.0
Initial Draft.
History
Draft Date
Sep. 2004
Remark
Preliminary
0.1
1) Correct part number ( change mode)
- 2A -> 1A (sequential row read : disable -> enable)
2) Correct Table.5 & Table 12
- Correct Command Set
- correct AC timing characteristics (tWP : 40 -> 25ns, tWH : 20 ->15ns)
3) Correct Summary description & page.7
- The cache feature is deleted in summary description.
Oct. 22. 2004
- Note.3 is deleted. (page.7)
4) Add System interface using CE don’t care (page. 38)
5) Change TSOP1, WSOP1,FBGA package dimension & figures.
- Change TSOP1, WSOP1, FBGA package mechanical data
- Change TSOP1, WSOP package figures
6) Correct TSOP1, WSOP1 Pin configuration
- 38th NC pin has been changed Lockpre (figure 2,3)
7) Add Bad block Management
1) LOCKPRE is changed to PRE
- Texts, Table and figures are changed.
2) Change Command set
- Read A,B are changed to Read1.
- Read C is changed to Read2.
3) Change AC, DC characterics
Preliminary
0.2
- tRB, tCRY, tCEH and tOH are added.
4) Correct Program time (max)
- before : 700us
- after
: 500us
5) Edit figures
- Address names are changed.
6) Change FBGA Package Dimension
- FD1 : 1.70(before) -> 0.90(after)
Mar. 08. 2005 Preliminary
Rev 1.3 / Jun. 2006
1
HY27US(08/16)121A Series
HY27SS(08/16)121A Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Revision History
Revision
No.
History
1) Change AC Characteristics (1.8V device)
tRC
before
after
50
60
tRP
25
40
tREH
15
20
tWC
50
60
tWP
25
40
tWH
15
20
tREA
30
40
- Continued
Draft Date
Remark
2) Change AC Parameter
0.3
Before
After
tCRY(3.3V)
50+tr(R/B#)
60+tr(R/B#)
tCRY(1.8V)
50+tr(R/B#)
80+tr(R/B#)
tOH
15
10
Jul. 08. 2005
Preliminary
3) Change Figure 20,22
4) Add Read ID Table
5) Change PAD Configuration
- GND is changed to VSS.
6) Add Marking Information
1) The test condition for I
CC1
operating current is corrected.
tCRY(3.3V)
Before
0.4
t
RC
=50ns,
CE#=
V
IL
,
I
OUT
=0mA
t
RC
(1.8V=60ns,
3.3V=50ns)
CE#=
V
IL
,
I
OUT
=0mA
Jul. 15. 2005
Preliminary
After
Rev 1.3 / Jun. 2006
2
HY27US(08/16)121A Series
HY27SS(08/16)121A Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Revision History
Revision
No.
History
1) The test conditions is corrected.
Test Conditions (
I
CC1)
Before
Test Conditions (
I
LI,
I
LO
)
VIN=VOUT=0 to 3.6V
- Continued
Draft Date
Remark
t
RC
=50ns
,
CE#=
V
IL
,
I
OUT
=
0mA
t
RC
(1.8V=60ns,
3.3V=50ns)
CE#=
V
IL
,
I
OUT
=
0mA
0.5
After
VIN=VOUT=(1.8V, 0 to 1.95V)
=(3.3V, 0 to 3.6V)
Jul. 20. 2005
Preliminary
2) Change VIL parameter (max.)
1.8V
Before
After
0.2xVcc
0.4
3.3V
0.2xVcc
0.8
1) Correct the test Conditions (DC Characteristics table)
Test Conditions (
I
LI,
I
LO
)
Before
VIN=VOUT=(1.8V, 0 to 1.95V)
=(3.3V, 0 to 3.6V)
VIN=VOUT=0 to Vcc (max)
0.6
After
Jul. 22. 2005
Preliminary
2) Change AC Conditions table
3) Add tWW parameter ( tWW = 100ns, min)
- Texts & Figures are added.
- tWW is added in AC timing characteristics table.
1) Edit Copy Back Program operation step
2) Edit System Interface Using CE don’t care Figures.
3) Change AC Characteristics (3.3V device)
0.7
before
after
tRP
30
25
tREA
35
30
Aug. 01. 2005
Preliminary
4) Correct Address Cycle Map.
1) Correct PKG dimension (TSOP, USOP PKG)
CP
0.8
Before
After
0.9
0.050
0.100
Nov. 07. 2005
Preliminary
Aug. 29. 2005
Preliminary
1) Correct USOP figure.
Rev 1.3 / Jun. 2006
3
HY27US(08/16)121A Series
HY27SS(08/16)121A Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
Revision History
Revision
No.
1.0
1.1
1.2
1) Delet Preliminary.
1) Correct Figure 32.
1) Add ECC algorithm. (1bit/512bytes)
2) Correct Read ID naming
1) Change AC Parameter
tWHR
- Continued
History
Draft Date
Nov. 08. 2005
Feb. 06. 2006
May. 09. 2006
Remark
1.3
Before
After
60 ns
50 ns
Jun. 20. 2006
Rev 1.3 / Jun. 2006
4
HY27US(08/16)121A Series
HY27SS(08/16)121A Series
512Mbit (64Mx8bit / 32Mx16bit) NAND Flash
FEATURES SUMMARY
HIGH DENSITY NAND Flash MEMORIES
- Cost effective solutions for mass storage applications
NAND INTERFACE
- x8 or x16 bus width.
- Multiplexed Address/ Data
- Pinout compatibility for all densities
FAST BLOCK ERASE
- Block erase time: 2ms (Typ.)
STATUS REGISTER
ELECTRONIC SIGNATURE
- 1st cycle : Manufacturer Code
- 2nd cycle: Device Code
SUPPLY VOLTAGE
- 3.3V device: VCC = 2.7 to 3.6V
: HY27USXX121A
CHIP ENABLE DON'T CARE
- Simple interface with microcontroller
AUTOMATIC PAGE 0 READ AT POWER-UP OPTION
- Boot from NAND support
- Automatic Memory Download
SERIAL NUMBER OPTION
HARDWARE DATA PROTECTION
- Program/Erase locked during Power transitions
DATA INTEGRITY
- 100,000 Program/Erase cycles
(with 1bit/512byte ECC)
- 10 years Data Retention
PACKAGE
- HY27(U/S)S(08/16)121A-T(P)
: 48-Pin TSOP1 (12 x 20 x 1.2 mm)
- HY27(U/S)S(08/16)121A-T (Lead)
- HY27(U/S)S(08/16)121A-TP (Lead Free)
- HY27(U/S)S(08/16)121A-S(P)
: 48-Pin USOP1 (12 x 17 x 0.65 mm)
- HY27(U/S)S(08/16)121A-S (Lead)
- HY27(U/S)S(08/16)121A-SP (Lead Free)
- HY27(U/S)S(08/16)121A-F(P)
: 63-Ball FBGA (9 x 11 x 1.0 mm)
- HY27(U/S)S(08/16)121A-F (Lead)
- HY27(U/S)S(08/16)121A-FP (Lead Free)
- 1.8V device: VCC = 1.7 to 1.95V : HY27SSXX121A
Memory Cell Array
= (512+16) Bytes x 32 Pages x 4,096 Blocks
= (256+8) Words x 32 pages x 4,096 Blocks
PAGE SIZE
- x8 device : (512 + 16 spare) Bytes
: HY27(U/S)S08121A
- x16 device: (256 + 8 spare) Words
: HY27(U/S)S16121A
BLOCK SIZE
- x8 device: (16K + 512 spare) Bytes
- x16 device: (8K + 256 spare) Words
PAGE READ / PROGRAM
- Random access: 3.3V: 12us (max.)
1.8V: 15us (max.)
- Sequential access: 3.3V device: 50ns (min.)
1.8V device: 60ns (min.)
- Page program time: 200us (typ.)
COPY BACK PROGRAM MODE
- Fast page copy without external buffering
Rev 1.3 / Jun. 2006
5
FPGA/CPLD
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